Anthony Warren Hill

US Patent:

6405351, Jun 11, 2002

Filed:

Jun 27, 2000

Appl. No.:

09/603708

Inventors:

Donald E. Steiss - Richardson TX
Anthony M. Hill - Dallas TX
Richard P. Wiley - Lucas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1750

US Classification:

716 5, 716 12

Abstract:

A computer system ( ). The computer system comprises processing circuitry ( ) and storage circuitry ( ) for storing a plurality of files. The plurality of files include a circuit description file ( ) comprising data describing devices and signals in a circuit. The plurality of files also include a plurality of list expressions ( ) relating to one of devices, signals, or devices and signals described by the data in the circuit description. Still further, the plurality of files also include a plurality of rules ( ). The processing circuitry is programmed to perform various steps. These steps include processing ( ) the plurality of list expressions to extract a plurality of lists in response to the circuit description. Each of the plurality of lists comprises a non-negative integer number of elements. The programmed steps further include processing ( ) the plurality of rules to evaluate one or more of the plurality of lists to verify connection accuracy within the circuit in response to the non-negative integer number of elements.

US Patent:

6492841, Dec 10, 2002

Filed:

Dec 3, 2001

Appl. No.:

09/998823

Inventors:

Anthony M. Hill - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 1900

US Classification:

326113, 326 16, 326112

Abstract:

A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below. When the scan-enable signal is equal to a logical one then the first output signal and the second output signal are either both equal to the scan-in signal or the first output signal is equal to a logical one and the second output signal is equal to the scan-in signal. When the scan-enable signal is equal to a logical zero, then the first output signal is equal to the first data signal and the second output signal is equal to the second data signal.

US Patent:

6493853, Dec 10, 2002

Filed:

Jul 17, 2000

Appl. No.:

09/617575

Inventors:

Nagaraj N. Savithri - Dallas TX
John Apostol - Plano TX
Anthony M. Hill - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 945

US Classification:

716 5, 716 6

Abstract:

In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic. Other instantiations of the cell are evaluated using the same multi-dimensional noise table.

US Patent:

6986089, Jan 10, 2006

Filed:

Sep 27, 2002

Appl. No.:

10/256723

Inventors:

Anthony M. Hill - Dallas TX, US
Richard D. Simpson - Bedford, GB

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/28
G06F 13/38

US Classification:

714726, 711109

Abstract:

In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.

US Patent:

7039823, May 2, 2006

Filed:

Apr 24, 2003

Appl. No.:

10/422275

Inventors:

Alan D. Hales - Richardson TX, US
Anthony M. Hill - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/12

US Classification:

713400, 713401, 713500

Abstract:

An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.

US Patent:

7318208, Jan 8, 2008

Filed:

Oct 17, 2005

Appl. No.:

11/251722

Inventors:

Usha Narasimha - Dallas TX, US
Anthony M. Hill - Dallas TX, US
Nagaraj Narasimh Savithri - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/50

US Classification:

716 5, 716 6

Abstract:

The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each node from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.

US Patent:

8547164, Oct 1, 2013

Filed:

Aug 25, 2011

Appl. No.:

13/218131

Inventors:

Jose Luis Flores - Richardson TX, US
Anthony M. Hill - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 35/00

US Classification:

327513

Abstract:

An integrated circuit is provided with a set of sensors for scaling voltage based on performance of the integrated circuit. The set of sensors are monitored, and sensor provides an output value indicative of a performance metric of the integrated circuit. The output values from the set of sensors are combined using a calibrated model to determine when a threshold value is reached. A change to an operating voltage for a portion of the integrated circuit is initiated in response to reaching the threshold.

US Patent:

7363604, Apr 22, 2008

Filed:

Sep 30, 2005

Appl. No.:

11/240924

Inventors:

Anthony M. Hill - Dallas TX, US
John Apostol - Plano TX, US
Usha Narasimha - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 5, 716 3, 716 4, 716 6

Abstract:

A novel approach to cross-talk analysis takes effective account of the nature of cross-talk interference. This approach employs conservative assumptions regarding (1) the equivalent output resistance, and (2) the definition of noise immunity for the victim gate. Also, this approach uses signal and noise current metrics in modeling the parameters of the active device elements. This approach provides an expectation of detection and elimination of noise hazards that might otherwise not be undetected.