Brian Douglas Reed

US Patent:

6924687, Aug 2, 2005

Filed:

Jul 29, 2003

Appl. No.:

10/630949

Inventors:

Brian Reed - San Jose CA, US
Puneet Sawhney - San Jose CA, US
Scott T. Becker - Darien IL, US

Assignee:

Artisan Components, Inc. - Sunnyvale CA

International Classification:

H03L005/00

US Classification:

327323, 361 911, 361 917, 361 939

Abstract:

An invention is disclosed for protecting an input buffer. A current from a p-supply to an input buffer is lowered when an input voltage to the input buffer is tolerant HIGH. The p-supply being a Vvoltage supplied to a p-channel transistor in the input buffer. In addition, the p-supply is set to a particular voltage when the input voltage to the input buffer is LOW, the particular voltage being at a specific value such that input transistors within the input buffer do not experience overstress voltages. Optionally, p-supply can be prevented from supplying current to the input buffer when an input voltage to the input buffer is tolerant HIGH.

US Patent:

8225239, Jul 17, 2012

Filed:

Jun 5, 2009

Appl. No.:

12/479674

Inventors:

Brian Reed - San Jose CA, US
Michael C. Smayling - Fremont CA, US
Joseph N. Hong - Cupertino CA, US
Stephen Fairbanks - Queen Creek AZ, US
Scott T. Becker - Scotts Valley CA, US

Assignee:

Tela Innovations, Inc. - Los Gatos CA

International Classification:

G06F 17/50

US Classification:

716 53, 716122, 716135

Abstract:

Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.

US Patent:

8448102, May 21, 2013

Filed:

Jun 9, 2009

Appl. No.:

12/481445

Inventors:

Stephen Kornachuk - San Jose CA, US
Carole Lambert - San Jose CA, US
James Mali - La Selva Beach CA, US
Brian Reed - San Jose CA, US
Scott T. Becker - Scotts Valley CA, US

Assignee:

Tela Innovations, Inc. - Los Gatos CA

International Classification:

G06F 17/50
G06F 9/455

US Classification:

716 55, 716118, 716119, 716123, 716132

Abstract:

Within a dynamic array architecture, an irregular wire layout region within a portion of a chip level layout is bracketed by placing first and second regular wire layout shapes on a first and second sides, respectively, of the irregular wire layout region. One or more irregular wire layout shapes are placed within the irregular wire layout region. A first edge spacing is maintained between the first regular wire layout shape and a first outer irregular wire layout shape within the irregular wire layout region nearest to the first regular wire layout shape. A second edge spacing is maintained between the second regular wire layout shape and a second outer irregular wire layout shape within the irregular wire layout region nearest to the second regular wire layout shape. The first and second edge spacings are defined to optimize lithography of the regular and irregular wire layout shapes.

US Patent:

20100031211, Feb 4, 2010

Filed:

Jul 30, 2009

Appl. No.:

12/512932

Inventors:

Brian Reed - San Jose CA, US
Michael C. Smayling - Fremont CA, US

Assignee:

Tela Innovations, Inc. - Campbell CA

International Classification:

G06F 17/50

US Classification:

716 7

Abstract:

Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

US Patent:

20120141407, Jun 7, 2012

Filed:

Sep 28, 2011

Appl. No.:

13/247138

Inventors:

Carla Dillon - Costa Mesa CA, US
Brian Reed - Huntington Beach CA, US
Talebi Mahin - Laguna Niguel CA, US

International Classification:

C02F 1/68
C01G 49/14
C01G 49/00
C01G 49/10

US Classification:

424 765, 423489, 423558, 423632

Abstract:

Compositions for the use of sewage or wastewater treatment, controlling odors or a combination thereof are disclosed, wherein the composition comprises at least one iron-based compound. Furthermore, methods of reducing the odors in a sewage or wastewater system are disclosed that include: adding a composition comprising at least one iron-based compound to a sewage or wastewater system. As used herein, the phrase “at least one iron-based compound” includes ferrous chloride, ferric chloride, ferrous sulfate, ferrate, polyferric sulfate, Ferix-3 (Fe(SO)3HO) or a combination thereof.

US Patent:

20140003120, Jan 2, 2014

Filed:

Jun 28, 2012

Appl. No.:

13/535802

Inventors:

Chihhung Liao - Fremont CA, US
Phu Nguyen - Dublin CA, US
Vimal R. Patel - Rochester MN, US
George F. Paulik - Rochester MN, US
Peder J. Paulson - Rochester MN, US
Brian J. Reed - Rochester MN, US
Salvatore N. Storino - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G11C 17/16
G06F 17/50

US Classification:

365 96, 716100

Abstract:

An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.

US Patent:

20140021999, Jan 23, 2014

Filed:

Jul 17, 2012

Appl. No.:

13/551012

Inventors:

Brian William REED - San Jose CA, US

Assignee:

ARM LIMITED - Cambridge

International Classification:

H03L 5/00

US Classification:

327333

Abstract:

Level shifting circuitry is provided for generating an output signal in response to an input signal. The level shifting circuitry includes a pulldown path for pulling the output signal to a lower output voltage level in response to a first transition of the input signal and a pullup path for pulling the output signal to a higher output voltage level in response to a second transition of the input signal. Pullup control circuitry places the pullup path in a non-conductive state in response to the output signal being pulled to the higher output voltage level. A keeper path keeps the output signal at the higher output voltage level while the pullup path is non-conductive until the pulldown path pulls the output signal low. A maximum drive current of the pulldown path is greater than a maximum drive current of the keeper path.

US Patent:

20210400296, Dec 23, 2021

Filed:

Jun 25, 2021

Appl. No.:

17/359335

Inventors:

- Irvine CA, US
Kyoungsoo Moon - Irvine CA, US
Brian Reed - Stamford CT, US
Zeev Neumeier - Berkeley CA, US

Assignee:

INSCAPE DATA, INC. - Irvine CA

International Classification:

H04N 19/467
G06T 1/00
H04N 1/32

Abstract:

Methods, devices, and computer-program products are provided for adding and decoding data to a digital video signal in a visually imperceptible manner. For example, an encoded video frame can be obtained, and one or more blocks of the encoded video frame can be decoded. Binary data can be added to a subset of pixels from a set of pixels of the one or more blocks. For instance, a pixel component can be modulated to add the binary data. The one or more blocks can be re-encoded using at least one coding mode. The re-encoded one or more blocks can be added to the encoded video frame.