Carl Osmond Gray

US Patent:

20220271951, Aug 25, 2022

Filed:

Feb 24, 2021

Appl. No.:

17/184396

Inventors:

- Santa Clara CA, US
Nikola Nedovic - San Jose CA, US
Carl Thomas Gray - Apex NC, US

Assignee:

NVIDIA Corp. - Santa Clara CA

International Classification:

H04L 9/32
H04L 9/08
H03K 19/17756
H03K 19/17704

Abstract:

A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

US Patent:

20220271952, Aug 25, 2022

Filed:

Sep 21, 2021

Appl. No.:

17/481154

Inventors:

- Santa Clara CA, US
Nikola Nedovic - San Jose CA, US
Carl Thomas Gray - Apex NC, US
Stephen G Tell - Chapel Hill NC, US

Assignee:

NVIDIA Corp. - Santa Clara CA

International Classification:

H04L 9/32
H04L 9/08

Abstract:

A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.

US Patent:

20210083836, Mar 18, 2021

Filed:

Jun 18, 2020

Appl. No.:

16/905635

Inventors:

- Santa Clara CA, US
Nikola Nedovic - San Jose CA, US
Carl Thomas Gray - Apex NC, US
Stephen G. Tell - Chapel Hill NC, US

Assignee:

NVIDIA Corp. - Santa Clara CA

International Classification:

H04L 7/00
H03K 3/037
H04B 1/12
H04B 1/16

Abstract:

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

US Patent:

20210083837, Mar 18, 2021

Filed:

Jul 13, 2020

Appl. No.:

16/927017

Inventors:

- Santa Clara CA, US
Nikola Nedovic - San Jose CA, US
Carl Thomas Gray - Apex NC, US
Stephen G Tell - Chapel Hill NC, US

Assignee:

NVIDIA Corp. - Santa Clara CA

International Classification:

H04L 7/00

Abstract:

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

US Patent:

20190173380, Jun 6, 2019

Filed:

Jan 15, 2019

Appl. No.:

16/248373

Inventors:

- Santa Clara CA, US
William J. Dally - Los Altos Hills CA, US
Carl Thomas Gray - Apex NC, US

International Classification:

H02M 3/158
H02M 1/08

Abstract:

A system and method are provided for controlling a modified buck converter circuit. A pull-up switching mechanism that is coupled to an upstream terminal of an inductor within a modified buck converter circuit is enabled. A load current at the output of the modified buck regulator circuit is measured. A capacitor current associated with a capacitor that is coupled to a downstream terminal of the inductor is continuously sensed and the pull-up switching mechanism is disabled when the capacitor current is greater than a sum of the load current and an enabling current value.

US Patent:

20170279355, Sep 28, 2017

Filed:

Mar 24, 2016

Appl. No.:

15/080461

Inventors:

- Santa Clara CA, US
William J. Dally - Los Altos Hills CA, US
Carl Thomas Gray - Apex NC, US

International Classification:

H02M 3/158
H02M 1/08

Abstract:

A system and method are provided for controlling a modified buck converter circuit. A pull-up switching mechanism that is coupled to an upstream terminal of an inductor within a modified buck converter circuit is enabled. A load current at the output of the modified buck regulator circuit is measured. A capacitor current associated with a capacitor that is coupled to a downstream terminal of the inductor is continuously sensed and the pull-up switching mechanism is disabled when the capacitor current is greater than a sum of the load current and an enabling current value.