Catherine L Chang

US Patent:

7613055, Nov 3, 2009

Filed:

Aug 9, 2007

Appl. No.:

11/836639

Inventors:

Catherine Chingi Chang - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 7/00

US Classification:

365194, 3652101, 36521012, 36523311

Abstract:

A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.

US Patent:

7839713, Nov 23, 2010

Filed:

Aug 31, 2007

Appl. No.:

11/897610

Inventors:

Haiming Yu - San Jose CA, US
Catherine Chingi Chang - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 8/00

US Classification:

36523005, 365203, 36518916

Abstract:

A memory circuit, where data is read from and written to the memory cell in one clock cycle via a port without pre-charging the port between reading data from and writing data to the memory cell via the port in the one clock cycle, is described. In one aspect, an embodiment of the present invention provides a memory circuit with a write control switch that has a voltage drop of substantially zero volts. In another aspect, an embodiment of the present invention provides a memory circuit with a write driver that uses a complementary metal oxide semiconductor (“CMOS”) inverter whose P-channel MOS (“PMOS”) transistor size is approximately 0. 5 times its N-channel MOS (“NMOS”) transistor size. In yet another aspect, an embodiment of the present invention provides a memory circuit with a latch-type read sense amplifier.

US Patent:

7916563, Mar 29, 2011

Filed:

Sep 22, 2009

Appl. No.:

12/564368

Inventors:

Catherine Chingi Chang - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 7/00

US Classification:

365194, 3652101, 36523311

Abstract:

A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.

US Patent:

8233340, Jul 31, 2012

Filed:

Mar 9, 2011

Appl. No.:

13/044032

Inventors:

Catherine Chingi Chang - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 7/00

US Classification:

365194, 36523311

Abstract:

A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.

US Patent:

8588015, Nov 19, 2013

Filed:

Jun 29, 2012

Appl. No.:

13/537111

Inventors:

Catherine Chingi Chang - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 7/00

US Classification:

365194, 36523311

Abstract:

A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.