Cheng Tung Huang

US Patent:

6777721, Aug 17, 2004

Filed:

Nov 14, 2002

Appl. No.:

10/298104

Inventors:

Cheng Huang - Cupertino CA
Yowjuang (Bill) Liu - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01C 2974

US Classification:

257111, 257112, 257122

Abstract:

The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small N P diode or a P N diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.

US Patent:

6785109, Aug 31, 2004

Filed:

Jan 8, 2001

Appl. No.:

09/756501

Inventors:

Cheng H. Huang - Cupertino CA
Chiakang Sung - Milpitas CA
John Costello - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H02H 322

US Classification:

361111, 361 56

Abstract:

A technique for providing ESD protection for integrated circuit devices with multiple power and/or ground buses is provided. The technique involves using a clamping device that is capable of handling both positive and negative ESD pulses to clamp each power bus, ground bus, and I/O pad within a device to a respective one of the ground buses. Without resorting to exhaustive cross-clamping, this arrangement provides a discharge path for an ESD pulse applied across any combination of power buses, ground buses, and I/O pads during an ESD event.

US Patent:

6794715, Sep 21, 2004

Filed:

Jul 3, 2002

Appl. No.:

10/189919

Inventors:

Yowjuang Liu - San Jose CA
Cheng Huang - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2976

US Classification:

257346, 257355

Abstract:

The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.

US Patent:

6897543, May 24, 2005

Filed:

Aug 22, 2003

Appl. No.:

10/646013

Inventors:

Cheng H. Huang - Cupertino CA, US
Yowjuang Liu - San Jose CA, US
Chih-Ching Shih - Pleasanton CA, US
Hugh Sung-Ki O - Fremont CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L029/00

US Classification:

257530, 257529, 257603, 257106, 257175, 438131, 438467, 438600, 438983

Abstract:

Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

US Patent:

7157782, Jan 2, 2007

Filed:

Feb 17, 2004

Appl. No.:

10/780427

Inventors:

Chih-Ching Shih - Pleasanton CA, US
Cheng H. Huang - Cupertino CA, US
Hugh Sung-Ki O - Fremont CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 29/00
H01L 29/04
H01L 29/10
H01L 31/036
H01L 23/58

US Classification:

257530, 257 50, 257798

Abstract:

Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.

US Patent:

7186610, Mar 6, 2007

Filed:

Aug 13, 2004

Appl. No.:

10/917699

Inventors:

Yowjuang (Bill) Liu - San Jose CA, US
Cheng Huang - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 21/8238

US Classification:

438234, 438202, 438305

Abstract:

The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.

US Patent:

7195958, Mar 27, 2007

Filed:

Jun 30, 2004

Appl. No.:

10/882874

Inventors:

Cheng Huang - Cupertino CA, US
Yowjuang (Bill) Liu - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 21/332

US Classification:

438133, 438134, 257 29181

Abstract:

The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small NP diode or a PN diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.

US Patent:

7272067, Sep 18, 2007

Filed:

Feb 18, 2005

Appl. No.:

11/060925

Inventors:

Cheng H. Huang - Cupertino CA, US
Yowjuang Liu - San Jose CA, US
Chih-Ching Shih - Pleasanton CA, US
Hugh Sung-Ki O - Fremont CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 17/18

US Classification:

3652257, 365 96, 257530, 257529, 257106, 438131, 438600, 438983, 438467

Abstract:

Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.