Chi Kin Chan

US Patent:

8041855, Oct 18, 2011

Filed:

Jan 27, 2009

Appl. No.:

12/360764

Inventors:

Jingzhao Ou - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 3/00
G06F 13/28
G06F 13/00
G06F 13/36

US Classification:

710 35, 710 14, 710 27, 710308

Abstract:

A system for communicating with a processor within an integrated circuit can include a dual-bus adapter () coupled to the processor () through a first communication channel () and a second communication channel (). The dual-bus adapter further can be coupled to a memory map interface () through which at least one peripheral device communicates with the processor. Single word operations can be exchanged between the processor and the dual-bus adapter through the first communication channel. Burst transfer operations can be performed by exchanging signaling information between the processor and the dual-bus adapter over the first communication channel and exchanging data words between the processor and the dual-bus adapter through the second communication channel.

US Patent:

8082530, Dec 20, 2011

Filed:

Feb 20, 2009

Appl. No.:

12/389468

Inventors:

Jingzhao Ou - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/455

US Classification:

716109, 716106

Abstract:

A computer-implemented method of estimating power usage for high-level blocks of a high-level modeling system (HLMS) circuit design can include generating a low-level circuit design from the HLMS circuit design. The method can include simulating the low-level circuit design and storing power usage data, from the simulating, for each of a plurality of circuit elements of the low-level circuit design. The circuit elements can be correlated with the high-level blocks of the HLMS circuit design. A power query of a selected block of the HLMS circuit design can be received and a measure of power usage for the selected high-level block can be determined according to the power usage data for selected ones of the plurality of circuit elements correlated with the selected high-level block. The measure of power usage for the selected high-level block can be output.

US Patent:

8145467, Mar 27, 2012

Filed:

Feb 25, 2008

Appl. No.:

12/036920

Inventors:

Jingzhao Ou - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 15

Abstract:

Method and apparatus for profiling a hardware/software embedded system are described. In one example, a hardware co-simulation interface is generated between a programmable logic device (PLD) configured with the embedded system and a computer based on a plurality of events. The embedded system in the PLD is simulated. During the simulation of the embedded system, occurrence of at least one event is detected to produce profiling data. The profiling data is stored into shared first-in-first-out (FIFO) logic of the PLD and the computer. The profiling data is retrieved from the shared FIFO logic at the computer.

US Patent:

8229725, Jul 24, 2012

Filed:

Sep 29, 2008

Appl. No.:

12/240874

Inventors:

Jingzhao Ou - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US
Shay Ping Seng - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/455

US Classification:

703 15, 703 25

Abstract:

Method and apparatus for modeling processor-based circuit models are described. Some examples relate to designing a circuit model having a processor system and custom logic. A bus adapter coupled to a bus of the processor system is generated. A shared memory interface between the custom logic and the bus adapter is generated. The shared memory interface includes a memory map for the processor system. A clock wrapper having a first clock input and a second clock input is generated. The first clock input drives the custom logic and first shared memory of the shared memory interface. The second clock input drives the processor system.

US Patent:

8265918, Sep 11, 2012

Filed:

Oct 15, 2009

Appl. No.:

12/579846

Inventors:

Hem C. Neema - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US
Kumar Deepak - San Jose CA, US
Nabeel Shirazi - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 14, 703 13

Abstract:

Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.

US Patent:

8417965, Apr 9, 2013

Filed:

Apr 7, 2010

Appl. No.:

12/755760

Inventors:

Arvind Sundararajan - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US
Nabeel Shirazi - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 11/30
G06F 12/14
G06F 7/04
G06F 17/30
G06F 9/445
H04L 29/06
H04L 9/00
H04L 9/30
H04K 1/00
H04N 7/16

US Classification:

713189, 713150, 713187, 380 30, 726 26, 717174

Abstract:

An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an encrypted core and a decryption key of the encrypted core. The decryption key is encrypted with an asymmetric cipher. The encrypted core is transmitted from the design tool to a trusted platform module. The decryption key is decrypted with a private key of the asymmetric cipher. The encrypted core is decrypted within the trusted platform module. One or more design tool operations are performed using the decrypted core.

US Patent:

8650019, Feb 11, 2014

Filed:

Jan 28, 2010

Appl. No.:

12/695800

Inventors:

Arvind Sundararajan - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 14, 703 13

Abstract:

Approaches for creating a timed hybrid simulation model for a circuit design specification. An untimed, high-level language (HLL) data-path model is input, along with an HLL data-path interface specification that specifies input ports of the HLL data-path model. A hardware description language (HDL) control-path model that specifies port attributes and associated stitching directives is generated. Each stitching directive specifies a control port and an associated one of the input ports of the HLL data-path model. The HLL data-path and HDL control-path models are linked () to create the timed hybrid simulation model, and the timed hybrid simulation model is stored in a processor-readable storage medium.

US Patent:

8650517, Feb 11, 2014

Filed:

Oct 19, 2009

Appl. No.:

12/581631

Inventors:

Arvind Sundararajan - Sunnyvale CA, US
Nabeel Shirazi - Saratoga CA, US
Jingzhao Ou - San Jose CA, US
Chi Bun Chan - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716104, 716101, 716139

Abstract:

Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.

Address:

12423 Leader St, Houston, TX 77072

VIN:

JN1BZ36A57M650173

Make:

NISSAN

Model:

350Z

Year:

2007