Christopher T Maxwell

US Patent:

7167038, Jan 23, 2007

Filed:

Nov 21, 2003

Appl. No.:

10/719399

Inventors:

Christopher T. Maxwell - Sherman TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 3/00

US Classification:

327407, 327108, 327112, 326 27, 326 57, 326 82, 326 83

Abstract:

A power efficiency control circuit eliminates short circuit power consumption associated with a CMOS output buffer in a manner that substantially increases the buffer operating efficiency. The technique is implemented to allow for a reduction of power associated with the output buffer pre-driver stage. The methodology employs a power efficiency control circuit that tri-states the output buffer before every transition.

US Patent:

7940505, May 10, 2011

Filed:

Dec 1, 2009

Appl. No.:

12/628880

Inventors:

Aline C. Sadate - Allen TX, US
Christopher T. Maxwell - Sherman TX, US
Nakshatra S. Gajbhiye - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 5/04
H02H 3/08
H02H 9/02
H02H 3/00
H02H 9/08

US Classification:

361 938, 361 78, 361 79, 361 87, 361 931, 361 939, 361103

Abstract:

Load switches are relatively common and in use with a variety of applications, and conventional load switches have been designed to have continually operating protection circuitry, which can consume a great deal of power. Here, a load switch integrated circuit (IC) is provided where a controller within the IC activates and deactivates various protection circuits in a sequence, allowing the protection circuit to protect the IC while also reducing power consumption.

US Patent:

20060139058, Jun 29, 2006

Filed:

Dec 29, 2004

Appl. No.:

11/025455

Inventors:

Christopher Maxwell - Sherman TX, US

International Classification:

H03K 19/00

US Classification:

326058000

Abstract:

An output buffer having a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level and controls the voltage at the gates of the first pull-up transistor and the first pull-down transistor to provide the logic level at the output node. A second pull-up transistor and a second pull-down transistor are connected in series between the two nodes of the power supply, their common connection node being connected to the output node. A control circuit provides an output indicating when the supply voltage is below a predetermined level. A control circuit is responsive to the output of the control circuit to control the voltage at the gates of the second pull-up transistor and the second pull-down transistor to provide the logic level at the output node only when the output of the control circuit indicates when the supply voltage is below the predetermined level.

US Patent:

20120274153, Nov 1, 2012

Filed:

Apr 28, 2011

Appl. No.:

13/096839

Inventors:

Christopher T. Maxwell - Sherman TX, US
John M. Perry - McKinney TX, US
Aline C. Sadate - Allen TX, US
James C. Spurlin - Sherman TX, US
Nakshatra S. Gajbhiye - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02J 1/00

US Classification:

307126

Abstract:

Conventionally, current detection in load switches is implemented by monitoring the voltage across a small value sense resistor in series with the load switch, where the differential voltage across is applied to a comparator to generate a control signal corresponding to a light load condition, a normal load condition, or an over-load condition. Detecting the light load condition, however, can be difficult to determine using this arrangement due to the low differential voltage. Here, however, a integrated circuit (IC) is provided that employs an internal voltage supply and comparators to examine the load current to determine whether a light load condition is present, which does not suffer from the same problems.