Christopher A Spence

US Patent:

6356340, Mar 12, 2002

Filed:

Nov 20, 1998

Appl. No.:

09/197020

Inventors:

Christopher A. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03B 2742

US Classification:

355 53, 430 5

Abstract:

A programmable reticle has a plurality of addressable pixels. Each of the pixels has one or more elastic elements which underlie a reflective surface, the elements each being activatable for selectively deforming part of the reflective surface. The amount of deformation is such that light reflected from a deformed part destructively interferes with light reflected from the vicinity of the deformed part. The programmable reticle may be used as a part of a scanning lithography system wherein a wafer or other device to be exposed is moved to expose different of its areas, while the pattern on the programmable reticle is changed to reflect the desired exposure pattern of the area of the wafer currently being exposed. In such a scanning system, any given point on the wafer will be exposed using a number of different pixels on the reticle; therefore the effect of a defective pixel will be âdilutedâ or âvoted outâ by the other, non-defective pixels also involved in exposing that spot.

US Patent:

6437348, Aug 20, 2002

Filed:

Oct 21, 1999

Appl. No.:

09/422310

Inventors:

Christopher F. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

A61N 500

US Classification:

2504912, 2504921

Abstract:

A device for exposing and heating a substrate coated with resist includes an exposure tool for selectively exposing the resist, and a heater for heating the exposed resist, the exposure tool and the heater able to simultaneously act on different portions of the resist. A method of patterning resist on a substrate includes the steps of selectively exposing the resist on the first portion of the substrate, heating the resist on the first portion, and simultaneously or thereafter selectively exposing the resist on a second portion of the substrate. In an exemplary embodiment the exposure tool is an electron beam generator for exposing a chemically-amplified resist, and the heater is a light source such as a laser light source which does not appreciably expose the resist. The device and method allow a post-exposure heating with a smaller delay between the exposure and the heating than with conventional methods, which involve exposing a reticle and mask completely before heating by baking.

US Patent:

6492066, Dec 10, 2002

Filed:

May 28, 1999

Appl. No.:

09/321089

Inventors:

Luigi Capodieci - Sunnyvale CA
Christopher A. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 900

US Classification:

430 5, 716 21

Abstract:

A method ( ) of characterizing optical proximity correction designs includes performing a mathematical transform ( ) on a first feature ( ) and a second feature ( ) each having a core portion ( ) and a first OPC design and a second OPC design applied thereto, respectively. The method ( ) further includes obtaining a metric (162) for the transformed first and second features, wherein the metric is based upon a capability of a pattern transfer system which will utilize masks employing the first and second features ( ) as a patterns thereon. One of the first feature or the second feature is then selected ( ) based upon an application of the metric to the first and second transformed features ( ), thereby selecting the one of the first feature or the second feature which provides for a better pattern transfer performance.

US Patent:

6562639, May 13, 2003

Filed:

Nov 6, 2001

Appl. No.:

09/993166

Inventors:

Anna Minvielle - San Jose CA
Luigi Capodieci - Santa Cruz CA
Christopher Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2166

US Classification:

438 14

Abstract:

In order to determine an amount of critical dimension variation to expect across a surface of a final production wafer, a plurality of test structures are formed on a test wafer. The test structures are preferably of a type commonly found on the final production wafer and may for example, include transistors, ring oscillators, resistors and/or diodes. Electrical parameter testing of the test structures is next conducted in order to obtain one or more electrical performance values for each test structure. For example, the electrical performance values may correspond to processing speed, drive current, and/or off-state current of the test structures. A correlation between the electrical performance values and expected critical dimension variations is then performed and a report is generated providing the expected critical dimension variations across the surface of the wafer. Expected critical dimension variations may be accounted for by varying characteristics of devices used during a photolithographic transfer process to the final production wafers.

US Patent:

6627355, Sep 30, 2003

Filed:

Dec 20, 2000

Appl. No.:

09/742970

Inventors:

Harry J. Levinson - Saratoga CA
Fan Piao - Fremont CA
Christopher A. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 900

US Classification:

430 5

Abstract:

The present invention provides a method of and system for reducing the absorption of light by opaque material in a photomask. The method includes providing a photomask substrate, and applying an opaque material to one side of the photomask substrate. The interface between the opaque material and photomask substrate reflects at least 80 percent of the light through the photomask.

US Patent:

6675369, Jan 6, 2004

Filed:

Dec 11, 2001

Appl. No.:

10/016702

Inventors:

Todd P. Lukanc - San Jose CA
Christopher A. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 21, 716 19, 430 4

Abstract:

A technique in which a boundary region is added to the outside parallel edge of phase zero (0) pattern defining polygons. This technique can reduce the need for optical proximity correction (OPC) and improve the manufacturability and patterning process window for integrated circuits. The technique can also set the width of both phase 0 and phase 180 polygons to specific sizes, making OPC easier to assign.

US Patent:

6749970, Jun 15, 2004

Filed:

Dec 11, 2001

Appl. No.:

10/016273

Inventors:

Todd P. Lukanc - San Jose CA
Christopher A. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 900

US Classification:

430 5

Abstract:

A technique in which a first boundary region is added to the ends of phase zero ( ) pattern defining polygons and a second boundary region is added to the ends of phase pattern. This technique can improve line end pattern definition and improve the manufacturability and patterning process window. The added boundary region balances the light on both sides of the line ends, resulting in a more predictable final resist pattern.

US Patent:

6749971, Jun 15, 2004

Filed:

Dec 11, 2001

Appl. No.:

10/016710

Inventors:

Todd P. Lukanc - San Jose CA
Christopher A. Spence - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 900

US Classification:

430 5

Abstract:

A mask generation method can enhance clear field phase shift masks using a chrome border around phase regions. An exemplary method involves identifying edges of a 180 degree phase pattern, expanding these edges, and merging the expansions with chrome. An alternative method involves oversizing and undersizing phase data, taking the difference, and merging the difference with chrome. The chrome region on the phase mask can improve mask generation by allowing the chrome on the mask to fully define the quartz etch.