Dan B Patterson

US Patent:

6976117, Dec 13, 2005

Filed:

Aug 13, 2002

Appl. No.:

10/218853

Inventors:

Lawrence T. Clark - Phoenix AZ, US
Dan W. Patterson - Scottsdale AZ, US
Stephen J. Strazdus - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/08

US Classification:

711 3, 711118

Abstract:

A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.

US Patent:

8397130, Mar 12, 2013

Filed:

Nov 25, 2009

Appl. No.:

12/626479

Inventors:

Lawrence T. Clark - Phoenix AZ, US
Dan W. Patterson - Scottsdale AZ, US
Xiaoyin Yao - Chandler AZ, US

Assignee:

Arizona Board of Regents for and on behalf of Arizona State University - Scottsdale AZ

International Classification:

G11C 29/00

US Classification:

714763

Abstract:

Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.

US Patent:

8397133, Mar 12, 2013

Filed:

Nov 25, 2009

Appl. No.:

12/626488

Inventors:

Lawrence T. Clark - Phoenix AZ, US
Dan W. Patterson - Scottsdale AZ, US
Xiaoyin Yao - Albuquerque NM, US
David Pettit - Gilbert AZ, US
Rahul Shringarpure - Calabasas CA, US

Assignee:

Arizona Board of Regents for and on behalf of Arizona State University - Scottsdale AZ

International Classification:

G06F 11/00

US Classification:

714766

Abstract:

Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.

US Patent:

8489919, Jul 16, 2013

Filed:

Nov 25, 2009

Appl. No.:

12/626495

Inventors:

Lawrence T. Clark - Phoenix AZ, US
Dan W. Patterson - Scottsdale AZ, US

Assignee:

Arizona Board of Regents - Scottsdale AZ

International Classification:

G06F 11/00

US Classification:

714 11, 714 10, 714 2

Abstract:

Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.

US Patent:

20050021925, Jan 27, 2005

Filed:

Jul 25, 2003

Appl. No.:

10/626968

Inventors:

Lawrence Clark - Phoenix AZ, US
Shay Demmons - Chandler AZ, US
Byungwoo Choi - Chandler AZ, US
Dan Patterson - Scottsdale AZ, US

International Classification:

G06F012/08

US Classification:

711203000, 711212000

Abstract:

A circuit to translate virtual addresses of varied page sizes into physical addresses enables selective access to an internally stored data in parallel to reading a specific physical address based on the input virtual address before the internally stored data matches in entirety for the address translation thereof. In one embodiment, a content addressed buffer may comprise at least two register files or static random access memories. For example, a banked architecture for a set associative translation lookaside buffer may reduce power consumption without compromising address translation speed.

US Patent:

20120306535, Dec 6, 2012

Filed:

Jun 4, 2012

Appl. No.:

13/487859

Inventors:

Lawrence T. Clark - Phoenix AZ, US
Nathan D. Hindman - Tempe AZ, US
Dan Wheeler Patterson - Scottsdale AZ, US

Assignee:

Arizona Board of Regents for and on behalf of Arizona State University - Scottsdale AZ

International Classification:

H03K 19/173
G06F 17/50

US Classification:

326 46, 716119, 716104

Abstract:

The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. TheSSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

US Patent:

20160065243, Mar 3, 2016

Filed:

Aug 27, 2015

Appl. No.:

14/837361

Inventors:

Dan Wheeler Patterson - Scottsdale AZ, US
Lawrence T. Clark - Phoenix AZ, US

Assignee:

Arizona Board of Regents on behalf of Arizona State University - Scottsdale AZ

International Classification:

H03M 13/11
G06F 9/30
H03M 13/00

Abstract:

This disclosure relates generally to processors and methods of operating the same. In particular, this disclosure relates to components for correcting soft errors in a processor. In one embodiment, a processor includes an instruction decoder and an exception handler. The instruction decoder is configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions. Additionally, an exception handler is configured to execute the one or more soft error correction instructions so as to correct one or more soft errors. In this manner, the processor is capable of correcting soft errors that are the result of radiation strikes.

US Patent:

20150363517, Dec 17, 2015

Filed:

Jun 15, 2015

Appl. No.:

14/739347

Inventors:

Lawrence T. Clark - Phoenix AZ, US
Dan Wheeler Patterson - Scottsdale AZ, US
Srivatsan Chellappa - Tempe AZ, US

Assignee:

Arizona Board of Regents on behalf of Arizona State University - Scottsdale AZ

International Classification:

G06F 17/50

Abstract:

This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.