Daniel T Pham

US Patent:

20130309846, Nov 21, 2013

Filed:

May 21, 2012

Appl. No.:

13/476552

Inventors:

Daniel T. Pham - Clifton Park NY, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 21/20

US Classification:

438478, 257E2109

Abstract:

Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon.

US Patent:

20130330916, Dec 12, 2013

Filed:

Jun 11, 2012

Appl. No.:

13/493021

Inventors:

Daniel T. Pham - Clifton Park NY, US
Robert J. Miller - Yorktown Heights NY, US
Kingsuk Maitra - San Jose CA, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 21/205

US Classification:

438504, 257E21101

Abstract:

Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.

US Patent:

20150187905, Jul 2, 2015

Filed:

Dec 30, 2013

Appl. No.:

14/143468

Inventors:

- Grand Cayman, KY
Ajey Poovannummoottil Jacob - Albany NY, US
Daniel T. Pham - Clifton Park NY, US
Mark V. Raymond - Schenectady NY, US
Christopher M. Prindle - Poughkeepsie NY, US
Catherine B. Labelle - Wappingers Falls NY, US
Linus Jang - Clifton Park NY, US
Robert Teagle - Hopewell Junction NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 29/66
H01L 29/06
H01L 29/78
H01L 29/51
H01L 29/423
H01L 21/768
H01L 21/3105
H01L 29/417

Abstract:

One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

US Patent:

20150076653, Mar 19, 2015

Filed:

Sep 17, 2013

Appl. No.:

14/028724

Inventors:

- Grand Cayman, KY
Andy Wei - Queensbury NY, US
Qi Zhang - Mechanicville NY, US
Richard J. Carter - Saratoga Springs NY, US
Hongliang Shen - Ballston Lake NY, US
Daniel Pham - Clifton Park NY, US
Sruthi Muralidharan - Troy NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 21/308
H01L 29/06
H01L 21/762

US Classification:

257506, 438424

Abstract:

Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

US Patent:

20150050792, Feb 19, 2015

Filed:

Aug 13, 2013

Appl. No.:

13/965258

Inventors:

- Grand Cayman, KY
Zhenyu Hu - Clifton Park NY, US
Andy Wei - Queensbury NY, US
Qi Zhang - Mechanicville NY, US
Nicholas V. LiCausi - Watervliet NY, US
Daniel Pham - Clifton Park NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 29/06
H01L 21/762

US Classification:

438296, 438430

Abstract:

Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench.

US Patent:

20150001628, Jan 1, 2015

Filed:

Jun 27, 2013

Appl. No.:

13/928947

Inventors:

- Grand Cayman, KY
Daniel Pham - Clifton Park NY, US
Andy Chi-Hung Wei - Queensbury NY, US
Zhenyu Hu - Clifton Park NY, US

International Classification:

H01L 27/088
H01L 21/762

US Classification:

257368, 438424

Abstract:

An improved structure and method for forming isolation between two adjacent field effect transistors is disclosed. A large substrate cavity is formed between gates of the two adjacent transistors. The substrate cavity is filled with an epitaxial material such as epitaxial silicon, silicon germanium, or III-V compound semiconductor to form an epitaxial region. A cavity is then formed in the epitaxial material, dividing the epitaxial region into two epitaxial regions that serve as source-drain regions.

US Patent:

20140273423, Sep 18, 2014

Filed:

Mar 13, 2013

Appl. No.:

13/798616

Inventors:

- Grand Cayman, KY
Jeremy A. Wahl - Delmar NY, US
Kerem Akarvardar - Saratoga Springs NY, US
Ajey P. Jacob - Albany NY, US
Daniel T. Pham - Clifton Park NY, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 29/66

US Classification:

438585, 977888

Abstract:

One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.