Daniel M Shepard

US Patent:

8526217, Sep 3, 2013

Filed:

Dec 3, 2012

Appl. No.:

13/692638

Inventors:

Daniel Shepard - North Billerica MA, US

Assignee:

Contour Semiconductor, Inc. - Billerica MA

International Classification:

G11C 11/00

US Classification:

365148, 365158, 365171, 365173

Abstract:

An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.

US Patent:

20050245069, Nov 3, 2005

Filed:

Apr 28, 2005

Appl. No.:

11/117118

Inventors:

Daniel Shepard - Salem NH, US

International Classification:

H01L021/4763

US Classification:

438626000

Abstract:

The present invention relates to the manufacture and processing of semiconductor wafers, and more particularly to methods for keeping the surface of a wafer flat during processing to improve lithography, planarization, and other process steps that benefit from a flatter wafer. The present invention is a means to disrupt the long-range stress across the surface of a wafer made of crystalline silicon or other materials so as to prevent distortions such as dishing of that wafer. To prevent such dishing or similar distortions, the long-range continuity of the film must be disrupted. The long-range continuity of the film can be disrupted simply by etching channels in the surface of the wafer. These etched channels could be incorporated into or combined with registration marks that might be etched initially on the wafer for the purpose of enabling a step and repeat lithography exposure tool to find each exposure point. To prevent long-range continuous films in the channels from having an effect, features in the channels at the intersections of horizontal and vertical channels can be incorporated to disrupt the continuous films therein.