Darlene A Hamilton

US Patent:

6344994, Feb 5, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/795849

Inventors:

Darlene G. Hamilton - San Jose CA
Yider Wu - Campbell CA
Michael Han - San Jose CA

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518505, 36518511, 257316

Abstract:

Dummy wordlines are provided between gaps of blocks of memory cells to compensate for higher charge loss at higher stress temperatures exhibited at edge wordlines of blocks of memory cells having large gaps. The dummy wordlines minimize the gap between the blocks. The dummy wordlines can be positioned between the blocks. Alternatively, the wordline width for the last block or sector wordline can be changed or different nitride used with less conductance in high temperatures. The dummy wordlines are typically ignored in normal operations on the memory.

US Patent:

6381550, Apr 30, 2002

Filed:

May 28, 1999

Appl. No.:

09/322195

Inventors:

Edward Hsia - Saratoga CA
Phuong K. Banh - Sunnyvale CA
Darlene Hamilton - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01N 3700

US Classification:

702 82, 36518511

Abstract:

A method of utilizing Fast Chip Erase to screen endurance rejects. Multiple sectors in a device are selected and a time necessary to program all cells in the sectors is monitored and if the monitored time exceeds a first time, the device fails. A time necessary to erase all the cells without any overerased cells is monitored and if the time exceeds a second time, the device fails. A time necessary to correct overerased cells is monitored and if the time exceeds a third time, the device fails. The total time from erase until overerase correction is achieved is monitored and if the total time exceeds a fourth time, the device fails. The total time to determine erasability is monitored and if this time exceeds a fifth time, the device fails.

US Patent:

6385093, May 7, 2002

Filed:

Mar 30, 2001

Appl. No.:

09/822995

Inventors:

Kazuhiro Kurihara - Sunnyvale CA
Feng Pan - Richmond CA
Weng Fook Lee - Santa Clara CA
Ravi Sunkavalli - Milpitas CA
Darlene Hamilton - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1604

US Classification:

36518529, 36518511, 36518519

Abstract:

A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.

US Patent:

6440789, Aug 27, 2002

Filed:

Nov 1, 2000

Appl. No.:

09/704026

Inventors:

Darlene Hamilton - San Jose CA
Len Toyoshiba - San Jose CA
Michael Fliesler - Santa Cruz CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218238

US Classification:

438232, 438258, 438275, 438279, 438307

Abstract:

A method of manufacturing a flash memory semiconductor device that eliminates the step of forming sidewall spacers on n-channel and p-channel transistor gate structures. Resist spacers having a dimension of G +2S are formed on n-channel transistor gate structures and an N implant is performed to form N implant is performed to form N regions in the n-channel substrate region. Resist spacers having a dimension of G +2S are formed on p-channel transistor gate structures and a P implant is performed to form P regions in the p-channel substrate region.

US Patent:

6442074, Aug 27, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/795854

Inventors:

Darlene G. Hamilton - San Jose CA
Kulachet Tanpairoj - Palo Alto CA
Ravi Sunkavalli - Santa Clara CA
Narbeh Derhacobian - Belmont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518529, 36518503, 36518522, 36518524, 36518528, 3651853

Abstract:

A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IOs together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.

US Patent:

6456533, Sep 24, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/796282

Inventors:

Darlene G. Hamilton - San Jose CA
Narbeh Derhacobian - Belmont CA
Janet S.Y. Wang - San Francisco CA
Kulachet K.T. Tanpairoj - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1134

US Classification:

36518522, 36518518

Abstract:

A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

US Patent:

6493261, Dec 10, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/795865

Inventors:

Darlene G. Hamilton - San Jose CA
Kulachet Tanpairoj - Palo Alto CA
Ravi Sunkavalli - Santa Clara CA
Narbeh Derhacobian - Belmont CA
Michael A. Van Buskirk - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518511, 36518533, 36518505

Abstract:

Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.

US Patent:

6493266, Dec 10, 2002

Filed:

Apr 9, 2001

Appl. No.:

09/829193

Inventors:

Santosh K. Yachareni - Santa Clara CA
Darlene G. Hamilton - San Jose CA
Binh Q. Le - San Jose CA
Kazuhiro Kurihara - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1134

US Classification:

36518522, 36518524

Abstract:

A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in association with a dual bit memory cell architecture. The method includes applying one reference voltage signal to the over erased core cell, and a different reference voltage signal to the reference cell, comparing the two currents produced by each, selectively verifying proper soft programming of one or more bits of the cell, determining that the dual bit memory cell is properly soft programmed. The method may also comprise selectively re-verifying proper soft programming of the cells after selectively soft programming at least one or more bits of the cell.