David E Horton

US Patent:

6397326, May 28, 2002

Filed:

Feb 16, 2001

Appl. No.:

09/788027

Inventors:

David C. Horton - Austin TX
Amit R. Gupta - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 944

US Classification:

712240, 712239, 712245, 711220, 711213

Abstract:

A method and circuit is provided for preloading a branch prediction unit within a microprocessor. In one embodiment of the method, a branch history storage device such as branch history shift register is written with a predetermined multibit predicter in response to the microprocessor receiving and executing a special write branch history storage device instruction for writing the predetermined multibit predicter into the branch history storage device. The branch history storage device is contained within a prediction circuit of the microprocessor, and generally the contents of the branch history storage device is used in the process of predicting the results of executing conditional branch instructions prior to their execution. Once the branch history storage device is preloaded with the predetermined multibit predicter, the prediction circuit predicts the result of a conditional branch instruction using the predetermined multibit predicter stored in the history device after the conditional branch instruction is received by the microprocessor and before the conditional branch instruction is executed. In one embodiment, the predetermined multibit predicter is an operand of the write history storage device instruction received and executed by the microprocessor.

US Patent:

6421696, Jul 16, 2002

Filed:

Aug 17, 1999

Appl. No.:

09/375458

Inventors:

David C. Horton - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1500

US Classification:

708404, 708409

Abstract:

A method for performing Fast (forward or inverse) Fourier Transform in a micro-processor-based computer system. The microprocessor includes parallel execution resources for executing parallel floating-point addition, subtractions and multiplication operations on the contents of a specialized set of internal registers. The method comprises performing computations associated with two adjacent butterflies simultaneously and in parallel. Thus, data operands are accessed, and computational results are stored, from/to memory in pairs. Furthermore, the ordering and arrangement of program instructions is optimized with respect to the execution resources available in the microprocessor. Care is taken to avoid potential stalling conditions. A processor simulator is used to anticipate and avoid potential resource conflicts. For example, instructions which require a common execution resource may be separated with one or more intervening instructions which utilize different execution resources.

US Patent:

6907438, Jun 14, 2005

Filed:

Mar 2, 2001

Appl. No.:

09/798660

Inventors:

David Horton - Austin TX, US
Yi Liu - Austin TX, US
Wei-Lien Hsu - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F017/14

US Classification:

708402, 708400

Abstract:

A method is disclosed for performing an inverse discrete cosine transform (IDCT) using a microprocessor having an instruction set that includes SIMD floating-point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating-point form so that the registers each hold two floating-point row data values; and (c) using SIMD floating-point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating-point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-IDCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-IDCT, two columns are preferably processed concurrently using SIMD instructions to improve computational efficiency. An intermediate buffer may be used to avoid unnecessary conversions between integer and floating-point format.

US Patent:

6973469, Dec 6, 2005

Filed:

Feb 1, 2001

Appl. No.:

09/776080

Inventors:

Wei-Lien Hsu - Austin TX, US
David Horton - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F017/14

US Classification:

708402, 708400

Abstract:

A method is disclosed for performing a discrete cosine transform (DCT) using a microprocessor having an instruction set that includes SIMD floating point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating point form so that the registers each hold two floating point row data values; and (c) using SIMD floating point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-DCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-DCT, two columns are preferably processed in parallel using SIMD instructions to improve computational efficiency. An intermediate buffer may be used to avoid unnecessary conversions between integer and floating point format.

US Patent:

20090015713, Jan 15, 2009

Filed:

Jul 7, 2008

Appl. No.:

12/217615

Inventors:

David C. Horton - Austin TX, US

International Classification:

H04N 11/20
G06K 9/00

US Classification:

348453, 382104, 348E05024

Abstract:

A method includes capturing an image and providing video frame data representative of the image in a first format. The video frame data in the first format includes a plurality of pixel data, the pixel data of each pixel containing single color data. The method also includes generating pixel data of a detection block representative of a subset of the video frame data using a homographic association of pixels of the detection block to the pixel data containing single color data, wherein the pixel data of each pixel of the detection block contains multiple color data. The method further contains providing the detection block to an image detection algorithm.

US Patent:

62232800, Apr 24, 2001

Filed:

Jul 16, 1998

Appl. No.:

9/116631

Inventors:

David C. Horton - Austin TX
Amit R. Gupta - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 932

US Classification:

712240

Abstract:

A method and circuit is provided for preloading a branch prediction unit within a microprocessor. In one embodiment of the method, a branch history storage device such as branch history shift register is written with a predetermined multibit predicter in response to the microprocessor receiving and executing a special write branch history storage device instruction for writing the predetermined multibit predicter into the branch history storage device. The branch history storage device is contained within a prediction circuit of the microprocessor, and generally the contents of the branch history storage device is used in the process of predicting the results of executing conditional branch instructions prior to their execution. Once the branch history storage device is preloaded with the predetermined multibit predicter, the prediction circuit predicts the result of a conditional branch instruction using the predetermined multibit predicter stored in the history device after the conditional branch instruction is received by the microprocessor and before the conditional branch instruction is executed. In one embodiment, the predetermined multibit predicter is an operand of the write history storage device instruction received and executed by the microprocessor.

US Patent:

52552390, Oct 19, 1993

Filed:

Aug 13, 1991

Appl. No.:

7/745073

Inventors:

Michael P. Taborn - Austin TX
Larry Metzger - Austin TX
David R. Horton - Apple Valley MN

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 700

US Classification:

365221

Abstract:

A multi-featured first-in-first-out (FIFO) memory device on a monolithic semiconductor integrated circuit chip. The FIFO device is bi-directional, in that the user may select the direction of data transfer through the device. The device may be configured in a transparent bypass mode of operation, wherein the FIFO memory array is bypassed, and data is transferred directed from either device input/output port to the other device input/output port. In another mode of operation allowing registered bypass operation, a byte of data may be written in an internal register from the device port being used to output data for later transfer to the device port presently being used to input data to the FIFO memory array. The FIFO device further includes a user-testable mode of operation, wherein data written into the FIFO memory array through a device input port may be read out of the same device input port. Device mode selection occurs through control pin slew detection, allowing mode selection with a minimum number of control pins.