David J Iverson

US Patent:

6557132, Apr 29, 2003

Filed:

Feb 22, 2001

Appl. No.:

09/791004

Inventors:

David V. Gangl - Essex Junction VT
Matthew Sean Grady - Burlington VT
David John Iverson - Underhill VT
Kenneth A. Lavallee - Colchester VT
Robert Edward Shearer - Richmond VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714736, 714732

Abstract:

A method for determining common failure modes of an integrated circuit device under test is disclosed. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs of the device under test. A set of output data generated by the device under test is then compared to a set of expected data, with the set of output data being generated by the device under test in response to the test pattern. It is then determined whether the set of output data has passed the test, with the set of output data passing the test if the set of output data matches the set of expected data. If the set of output data has not passed the test, then it is determined whether an output signature corresponding to the set of output data matches a previously stored output signature. Fail data corresponding to the output signature is then stored if the output signature matches a previously stored output signature.

US Patent:

6754864, Jun 22, 2004

Filed:

Feb 22, 2001

Appl. No.:

09/791003

Inventors:

David V. Gangl - Essex Junction VT
Matthew Sean Grady - Burlington VT
David John Iverson - Underhill VT
Gary William Maier - Burlington VT
Robert Edward Shearer - Richmond VT
Donald Lawrence Wheater - Hinesburg VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714733, 714732

Abstract:

A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether the generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.