Drew William Delaney

US Patent:

8319318, Nov 27, 2012

Filed:

Apr 6, 2010

Appl. No.:

12/755201

Inventors:

Ravi K Nalla - Chandler AZ, US
Drew Delaney - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/552
H01L 23/34

US Classification:

257660, 257659, 257665, 257783, 257728, 257E23178

Abstract:

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.

US Patent:

8507324, Aug 13, 2013

Filed:

Oct 25, 2012

Appl. No.:

13/660095

Inventors:

Ravi K Nalla - San Jose CA, US
Drew W Delaney - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/58
H01L 21/50

US Classification:

438118, 438125, 257E21505, 257E21499

Abstract:

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.

US Patent:

8618652, Dec 31, 2013

Filed:

Apr 16, 2010

Appl. No.:

12/761782

Inventors:

Ravi K Nalla - Chandler AZ, US
John S Guzek - Chandler AZ, US
Javier Soto Gonzalez - Chandler AZ, US
Drew W Delaney - Chandler AZ, US
Hamid R Azimi - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/053

US Classification:

257700, 257706, 257E2302, 257E23023, 438121, 438122, 438123, 438125

Abstract:

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

US Patent:

20030183416, Oct 2, 2003

Filed:

Mar 29, 2002

Appl. No.:

10/113026

Inventors:

Jerry White - Glendale AZ, US
Scott Lindsey - Brentwood CA, US
Drew Delaney - Gilbert AZ, US

International Classification:

H05K001/18
H05K003/30

US Classification:

174/257000, 174/260000, 029/842000, 029/840000

Abstract:

A method of electrically coupling a first substrate () and a second substrate () includes forming a conductive bump () on the first substrate () by electroless plating a metal and nonconductive particles () together. The first substrate () and the second substrate () are bonded with a nonconductive polymer () so that the conductive bump () and a conductive pad () of the second substrate ) are electrically coupled.

US Patent:

20050118748, Jun 2, 2005

Filed:

Dec 1, 2003

Appl. No.:

10/725782

Inventors:

Mahesh Sambasivam - Pennington NJ, US
Drew Delaney - Gilbert AZ, US
Saeed Shojaie - Gilbert AZ, US

International Classification:

H01L021/44
H01L021/48
H01L021/50

US Classification:

438106000

Abstract:

Method of forming microeletronic devices by disposing a radiation curable underfill material or adhesive material between a substrate and a microelectronic die, and exposing any the radiation curable material which bleeds-out therefrom to radiation before or immediately after disposition, thereby reducing the extent of material bleed-out.

US Patent:

20110316140, Dec 29, 2011

Filed:

Jun 29, 2010

Appl. No.:

12/825729

Inventors:

Ravi K. Nalla - San Jose CA, US
Mathew J. Manusharow - Phoenix AZ, US
Drew Delaney - Chandler AZ, US

International Classification:

H01L 23/538
H01L 21/60
H01L 23/48

US Classification:

257698, 438121, 257E21506, 257E23011, 257E23169

Abstract:

A microelectronic package includes a substrate (), a die () embedded within the substrate, the die having a front side () and a back side () and a through-silicon-via () therein, build-up layers () built up over the front side of the die, and a power plane () in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (), a first die () and a second die () embedded in the substrate and having a front side () and a back side () and a through-silicon-via () therein, build-up layers () over the front sides of the first and second dies, and an electrically conductive structure () in physical contact with the back sides of the first and second dies.

US Patent:

20120074581, Mar 29, 2012

Filed:

Sep 24, 2010

Appl. No.:

12/890082

Inventors:

John S. Guzek - Chandler AZ, US
Ravi K. Nalla - San Jose CA, US
Javier Soto Gonzalez - Chandler AZ, US
Drew Delaney - Chandler AZ, US
Suresh Pothukuchi - Chandler AZ, US
Mohit Mamodia - Chandler AZ, US
Edward Zarbock - Gilbert AZ, US
Johanna M. Swan - Scottsdale AZ, US

International Classification:

H01L 23/538
H01L 21/50

US Classification:

257774, 438107, 257E23174, 257E21499

Abstract:

An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

US Patent:

20130003319, Jan 3, 2013

Filed:

Jun 30, 2011

Appl. No.:

13/173327

Inventors:

PRAMOD MALATKAR - Chandler AZ, US
DREW W. DELANEY - Chandler AZ, US

International Classification:

H05K 7/00
B32B 38/10
B05D 5/12

US Classification:

361746, 427 58, 427123, 156247, 361728

Abstract:

The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.