Frank K Cheung

US Patent:

7304675, Dec 4, 2007

Filed:

Jun 10, 2003

Appl. No.:

10/458339

Inventors:

Frank N. Cheung - Agoura Hills CA, US
Robert J. Coda - Torrance CA, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

H04N 5/33
H04N 3/14
H04N 5/335

US Classification:

348305, 348164, 348166

Abstract:

A system () and method for outputting data from a detector (). The novel system () includes a first controller () that samples the detector () at a first rate, a memory () for storing the sampled data, and a second controller () that outputs data from the memory () at a second rate. In a illustrative embodiment, the first rate is symmetrical from field to field, while the second rate is asymmetrical from field to field.

US Patent:

7388603, Jun 17, 2008

Filed:

Jun 10, 2003

Appl. No.:

10/457934

Inventors:

Frank N. Cheung - Agoura Hills CA, US
Hector Q. Gonzalez - Torrance CA, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

H04N 5/228
H04N 5/217
H04N 9/64

US Classification:

34820814, 3482084, 3482086, 348241, 348248

Abstract:

An imaging system disables pixel integration for images within frames that are identified as moving while enables pixel integration for images that are not moving. The system may implement a frame-averaging type of integration or recursive types of frame integration, or may refrain from performing frame integration. On a pixel-by-pixel basis, the system may compare a pixel from frame memory with a corresponding pixel of an input frame and may disable pixel integration for the pixel when a difference between the compared pixels exceeds a threshold. One of the integration processes may be performed on the pixels when the difference does not exceed the threshold. When frame integration is disabled or de-selected (e. g. , for pixels having motion), the frame memory may be bypassed and a self-integration may be performed with corresponding pixels from a current frame effectively resulting in no integration. Some embodiments may use multiple thresholds, and may use different integration algorithms depending on conditions within a scene.

US Patent:

20040268030, Dec 30, 2004

Filed:

May 12, 2004

Appl. No.:

10/844284

Inventors:

Frank Cheung - Agoura Hills CA, US

International Classification:

G06F012/00

US Classification:

711/105000, 711/167000

Abstract:

An efficient memory controller. The controller includes a first mechanism for associating one or more input command sequences with one or more corresponding values. A second mechanism selectively sequences one of the one or more command sequences to a memory in response to a signal. A third mechanism compares each of the one or more values to a state of the second mechanism and provides the signal in response thereto. In a specific embodiment, the one or more corresponding values are execution time code values, and the second mechanism includes a sequencer state machine that provides the state of the second mechanism as a sequencer time code. In the specific embodiment, a compare module compares the sequencer time code to a time code associated with a next available command sequence and execution time code pair and provides the signal in response thereto.

US Patent:

20040268173, Dec 30, 2004

Filed:

Jun 30, 2003

Appl. No.:

10/611114

Inventors:

Frank Cheung - Agoura Hills CA, US
Richard Chin - Torrance CA, US

International Classification:

G06F001/12

US Classification:

713/400000

Abstract:

A system and method for aligning an input signal () synchronized to a first clock signal () with a second clock signal (). The invention includes a mechanism () for generating a third clock signal () and an arrangement () for loading the input signal () in accordance with the third clock signal () and reading out an output signal in accordance with the second clock signal (). In an illustrative embodiment, the invention is used in a sensor system () to align detector input data (), which is synchronized to a data-capture clock (), with a signal-processing clock (). The register () acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system () clocks in the sampled data.

US Patent:

20050023469, Feb 3, 2005

Filed:

Jul 28, 2003

Appl. No.:

10/629042

Inventors:

Richard Chin - Torrance CA, US
Frank Cheung - Agoura Hills CA, US
Eric Sutton - Los Angeles CA, US

International Classification:

G01J005/02

US Classification:

250352000

Abstract:

A system and method for stabilizing the temperature of a detector array. The novel invention () includes one or more video reference pixels () adapted to output a reference signal that is responsive to the temperature of the detector array (), and a mechanism for adjusting the temperature of the detector array () based on the reference signal. In the illustrative embodiment, the mechanism includes a thermal electric cooler () and a processor () running a control algorithm () which calculates the amount of current which should be applied to the thermal electric cooler () based on the reference signal from the video reference pixels (). The video reference pixels () are constructed from the same substrate as the detector array (), but are constructed in a manner such that they do not respond to changes in scene illumination.

US Patent:

20050033875, Feb 10, 2005

Filed:

Jun 28, 2004

Appl. No.:

10/878893

Inventors:

Frank Cheung - Agoura Hills CA, US
Richard Chin - Torrance CA, US

International Classification:

G06F003/00

US Classification:

710029000

Abstract:

A system for selectively affecting data flow to and/or from a memory device. The system includes a first mechanism for intercepting data bound for the memory device or originating from the memory device. A second mechanism compares a data level associated with the first mechanism to one or more thresholds and provides a signal in response thereto. A third mechanism selectively releases data from the first mechanism or from the memory device in response to the signal. In the specific embodiment, the first mechanism includes one or more First-In-First-Out (FIFO) memory buffers having level indicators that provide data level information. The third mechanism includes a memory manager that provides the signal to the one or more FIFO buffers or to the memory device based on the data level information, thereby causing the one or more FIFO buffers to release the data or accept data from the memory device.

US Patent:

20060279341, Dec 14, 2006

Filed:

Aug 22, 2006

Appl. No.:

11/507677

Inventors:

Frank Cheung - Agoura Hills CA, US
Richard Chin - Torrance CA, US

International Classification:

H03L 7/00

US Classification:

327141000

Abstract:

A system and method for aligning an input signal () synchronized to a first clock signal () with a second clock signal () The invention includes a mechanism () for generating a third clock signal () and an arrangement () for loading the input signal () in accordance with the third clock signal () and reading out an output signal in accordance with the second clock signal (). In an illustrative embodiment, the invention is used in a sensor system () to align detector input data (), which is synchronized to a data-capture clock (), with a signal-processing clock (). The register () acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system () clocks in the sampled data.

US Patent:

20140028479, Jan 30, 2014

Filed:

Jul 17, 2013

Appl. No.:

13/944819

Inventors:

Frank N.G. Cheung - Agoura CA, US

International Classification:

H03M 7/30

US Classification:

341 87

Abstract:

A data translation system and method. This invention provides a reverse approach to implement a M bit input to N bit output cumulative/monotonic transfer function, (where M>N) by a (2**N)×M bit memory instead of the conventional (2**M)×N bit memory. The invention offers substantial circuit size savings without compromising on transfer function resolution and is independent of transfer function mapping algorithms. The M bit memory content of the reverse LUT contains input video group information for each output level and the (2**N) addresses of the reverse LUT represent the corresponding transfer function output levels. This data to address representation of the input to output relationship is exactly opposite to the conventional address to data format. Search and compare methods are employed to locate the input video group that the incoming video belongs to and the associated address of the reverse LUT represents the output.