Gregory Thomas Lynch

US Patent:

20230008489, Jan 12, 2023

Filed:

Jul 8, 2021

Appl. No.:

17/370894

Inventors:

- San Diego CA, US
Reza JALILIZEINALI - San Marcos CA, US
Sreeker DUNDIGAL - San Diego CA, US
Krishna Chaitanya CHILLARA - Del Mar CA, US
Gregory LYNCH - San Diego CA, US

International Classification:

H02H 9/04
H01L 27/02

Abstract:

An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad. The gate pull transistor may be configured to provide a low impedance path between the gate of the driver transistor and the I/O pad or the first rail when an overvoltage signal applied to the I/O pad has a magnitude that exceeds the nominal operating range of voltage levels defined for the I/O pad.