Gregory F Lynch

US Patent:

20230008489, Jan 12, 2023

Filed:

Jul 8, 2021

Appl. No.:

17/370894

Inventors:

- San Diego CA, US
Reza JALILIZEINALI - San Marcos CA, US
Sreeker DUNDIGAL - San Diego CA, US
Krishna Chaitanya CHILLARA - Del Mar CA, US
Gregory LYNCH - San Diego CA, US

International Classification:

H02H 9/04
H01L 27/02

Abstract:

An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad. The gate pull transistor may be configured to provide a low impedance path between the gate of the driver transistor and the I/O pad or the first rail when an overvoltage signal applied to the I/O pad has a magnitude that exceeds the nominal operating range of voltage levels defined for the I/O pad.

US Patent:

20160308519, Oct 20, 2016

Filed:

Apr 25, 2016

Appl. No.:

15/138142

Inventors:

- San Diego CA, US
Alvin Leng Sun Loke - San Diego CA, US
Stephen Knol - San Diego CA, US
Gregory Francis Lynch - San Diego CA, US
Tin Tin Wee - San Diego CA, US
LuVerne Ray Peterson - San Diego CA, US
Yue Li - San Diego CA, US

International Classification:

H03K 5/15
H01L 23/538
H01L 25/065

Abstract:

Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

US Patent:

20160294383, Oct 6, 2016

Filed:

Jul 6, 2015

Appl. No.:

14/792441

Inventors:

- San Diego CA, US
Jacob Stephen Schneider - San Diego CA, US
Thomas Clark Bryan - Carlsbad CA, US
LuVerne Ray Peterson - San Diego CA, US
Gregory Francis Lynch - San Diego CA, US
Alvin Leng Sun Loke - San Diego CA, US

International Classification:

H03K 17/687

Abstract:

A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

US Patent:

20160020759, Jan 21, 2016

Filed:

Jul 18, 2014

Appl. No.:

14/335681

Inventors:

- San Diego CA, US
Alvin Leng Sun Loke - San Diego CA, US
Stephen Knol - San Diego CA, US
Gregory Francis Lynch - San Diego CA, US
Tin Tin Wee - San Diego CA, US
LuVerne Ray Peterson - San Diego CA, US
Yue Li - San Diego CA, US

International Classification:

H03K 5/15
H01L 23/538

Abstract:

Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.