Guang Qun Chen

US Patent:

8098076, Jan 17, 2012

Filed:

Apr 1, 2009

Appl. No.:

12/416375

Inventors:

Guang Chen - San Jose CA, US
Charles Miller - Fremont CA, US
David Pritzkau - Brentwood CA, US

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 31/20

US Classification:

32475407, 32475411

Abstract:

Apparatus for terminating a test signal applied to multiple semiconductor loads under test is described—for example apparatus for interfacing a test signal between a tester and a semiconductor device under test (DUT). In some examples, a probe card assembly may include at least one probe substrate each having test probes configured to contact test features of a DUT; a wiring substrate, coupled to the at least one probe substrate, having a connector configured for coupling with a source termination of a tester; a signal path formed on and/or in the wiring substrate and the at least one probe substrate, the signal path having a trace and trace stubs fanning out from the trace, an input of the trace being coupled to the connector and outputs of the trace stubs being coupled to the test probes; and a resistive termination coupled between the trace and at least one potential.

US Patent:

20050233337, Oct 20, 2005

Filed:

Apr 19, 2004

Appl. No.:

10/828357

Inventors:

Bill Peck - Mountain View CA, US
Eric Leproust - San Jose CA, US
David Adaskin - San Jose CA, US
Guang Chen - San Jose CA, US
William Chesk - San Jose CA, US
Donald Schremp - San Jose CA, US
Stanley Woods - Cupertino CA, US

International Classification:

C12Q001/68
C12M001/34
B05D003/00

US Classification:

435006000, 435287200, 427002110

Abstract:

Methods and devices for fabricating a chemical array are provided. Embodiments include determining a chemical array layout in which each feature in the layout has a size that is chosen based on its composition and fabricating a chemical array according to the chemical array layout. In certain embodiments, at least two features of an array fabricated according to the subject methods are of different sizes. Embodiments also include chemical arrays having features of different sizes, e.g., fabricated according to the subject methods. Also provided are embodiments that include fluid deposition devices capable of fabricating chemical arrays having features of different sizes, e.g., for use in practicing the subject methods. Algorithms present on computer readable mediums for use in practicing the subject methods may also be provided in certain embodiments. Embodiments of the subject invention may also include systems and kits for use in practicing the subject methods.

US Patent:

20220335190, Oct 20, 2022

Filed:

Jul 1, 2022

Appl. No.:

17/856776

Inventors:

Guang Chen - Fremont CA, US
Yuet Li - Fremont CA, US
Archanna Srinivasan - San Jose CA, US

International Classification:

G06F 30/347

Abstract:

Systems or methods of the present disclosure may provide for determining a load line for operation of a programmable logic fabric where the load line is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The load line may be determined using software modeling for the design or configuration. Additionally or alternatively, the load line may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

US Patent:

20210313989, Oct 7, 2021

Filed:

Jun 21, 2021

Appl. No.:

17/353549

Inventors:

- Santa Clara CA, US
Guang Chen - Fremont CA, US
Venu Kondapalli - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19/1778
H03K 21/08

Abstract:

An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.

US Patent:

20210036705, Feb 4, 2021

Filed:

Oct 19, 2020

Appl. No.:

17/074245

Inventors:

- Santa Clara CA, US
Guang Chen - San Jose CA, US
Wendemagegnehu T. Beyene - San Jose CA, US
Ravi Prakash Gutala - San Jose CA, US

International Classification:

H03K 19/17772
H01L 25/18
H01L 23/538
H01L 23/00
G06F 30/34

Abstract:

A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.

US Patent:

20210004032, Jan 7, 2021

Filed:

Sep 24, 2020

Appl. No.:

17/031446

Inventors:

- Santa Clara CA, US
Archanna Srinivasan - San Jose CA, US
Guang Chen - Fremont CA, US
Janani Chandrasekhar - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 1/56
H03K 19/17736
H03K 17/22

Abstract:

An electronic system includes first, second, third, and fourth integrated circuit dies. The third integrated circuit die has a first voltage regulator circuit. A supply voltage output of the first voltage regulator circuit is coupled to provide a first supply voltage to a supply voltage input of the first integrated circuit die. The first voltage regulator circuit generates a first power ready signal that indicates when the first supply voltage has reached a first threshold voltage. The fourth integrated circuit die has a second voltage regulator circuit that generates a second supply voltage in response to the first power ready signal. A supply voltage output of the second voltage regulator circuit is coupled to provide the second supply voltage to a supply voltage input of the second integrated circuit die.

US Patent:

20210004643, Jan 7, 2021

Filed:

Jul 2, 2019

Appl. No.:

16/460192

Inventors:

- Sunnyvale CA, US
Guang CHEN - Sunnyvale CA, US
Weide ZHANG - Sunnyvale CA, US
Yuliang GUO - Sunnyvale CA, US
Ka Wai TSOI - Sunnyvale CA, US

International Classification:

G06K 9/62
G06K 9/00

Abstract:

A list of images is received. The images were captured by a sensor of an ADV chronologically while driving through a driving environment. A first image of the images is identified that includes a first object in a first dimension (e.g., larger size) detected by an object detector using an object detection algorithm. In response to the detection of the first object, the images in the list are traversed backwardly in time from the first image to identify a second image that includes a second object in a second dimension (e.g., smaller size) based on a moving trail of the ADV represented by the list of images. The second object is then labeled or annotated in the second image equivalent to the first object in the first image. The list of images having the labeled second image can be utilized for subsequent object detection during autonomous driving.

US Patent:

20200406893, Dec 31, 2020

Filed:

Jun 28, 2019

Appl. No.:

16/457847

Inventors:

- Sunnyvale CA, US
Guang CHEN - Sunnyvale CA, US
Weide ZHANG - Sunnyvale CA, US
Yuliang GUO - Sunnyvale CA, US
Ka Wai TSOI - Sunnyvale CA, US

International Classification:

B60W 30/095
B60W 30/09
G06K 9/00
G05D 1/00

Abstract:

During the autonomous driving, the movement trails or moving history of obstacles, as well as, an autonomous driving vehicle (ADV) may be maintained in a corresponding buffer. For each of the obstacles or objects and the ADV, the vehicle states at different points in time are maintained and stored in one or more buffers. The vehicle states representing the moving trails or moving history of the obstacles and the ADV may be utilized to reconstruct a history trajectory of the obstacles and the ADV, which may be used for a variety of purposes. For example, the moving trails or history of obstacles may be utilized to determine lane configuration of one or more lanes of a road, particularly, in a rural area where the lane markings are unclear. The moving history of the obstacles may also be utilized predict the future movement of the obstacles, tailgate an obstacle, and infer a lane line.