James L Rhodes

US Patent:

6363504, Mar 26, 2002

Filed:

Aug 31, 1999

Appl. No.:

09/386945

Inventors:

James Vernon Rhodes - Chandler AZ
Robert David Conklin - Chandler AZ
Timothy Allen Barr - Chandler AZ

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01B 3128

US Classification:

714724, 714 30, 714726, 714731, 714738, 702118, 3241581, 324 765

Abstract:

A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and in response, the control circuit passes the clock signal from the first input to only certain outputs which the commands select. All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested; and so in response to the programmable commands, the clock signal is sent sequentially to the chips that are to be tested, in selectable subsets. By such sequencing, the total power dissipation of the chips that are tested can be regulated when the chips are of a type that dissipate a large amount of power when they receive the clock signal, but dissipate substantially less power when they do not receive the clock signal.

US Patent:

6363510, Mar 26, 2002

Filed:

Aug 31, 1999

Appl. No.:

09/386946

Inventors:

James Vernon Rhodes - Chandler AZ
Robert David Conklin - Chandler AZ
Timothy Allen Barr - Chandler AZ

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R 3128

US Classification:

714738, 714 30, 714726, 702118, 3241581, 324765

Abstract:

A system for testing integrated circuit chips is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams that are readable one word at a time. In operation, each pattern generator selectively reads the bit streams, word by word, from its respective memory; and its sends the words that are read to all of the chip driver circuits which are coupled to its separate bus, simultaneously. While that is occurring, each chip driver converts the words which it is sent into bit serial test signals which test multiple integrated circuit chips in parallel. Since all of the pattern generators operate in parallel, and since each pattern generator sends bit streams to all of the chip driver circuits that are coupled to its bus simultaneously, a high speed of operation is attained.

US Patent:

6405150, Jun 11, 2002

Filed:

Aug 31, 1999

Appl. No.:

09/387197

Inventors:

James Vernon Rhodes - Chandler AZ
Robert David Conklin - Chandler AZ
Timothy Allen Barr - Chandler AZ

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G11C 700

US Classification:

702123, 702117, 714741, 714724, 714730, 365201

Abstract:

A system for testing integrated circuit chips is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. If the code indicates that the number of bit streams in a set is only one, then that one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more than one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary. Each series of unused bits causes the next bit stream to start on a word boundary; and, that simplifies the circuitry which the pattern generator uses to address the bit streams.

US Patent:

6415408, Jul 2, 2002

Filed:

Nov 3, 1999

Appl. No.:

09/432965

Inventors:

James Vernon Rhodes - Chandler AZ
Robert David Conklin - Chandler AZ

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1100

US Classification:

714738, 711206

Abstract:

A multi-stage algorithmic pattern generator, which generates bit streams for testing IC chips, is comprised of an initial stage, an intermediate stage, and an output stage which are coupled together as a three stage pipeline. The initial stage sequentially generates multiple sets of virtual addresses for a virtual memory in response to a series of instructions from an external source. The intermediate stage sequentially stores each set of virtual addresses from the initial stage and translates the stored set of virtual addresses into a set of physical addresses for an actual memory that is to be tested. The output stage sequentially stores each set of physical addresses from the intermediate stage and generates output signals for testing the memory chips, by selecting bits from the stored set of physical addresses.

US Patent:

6415409, Jul 2, 2002

Filed:

Nov 3, 1999

Appl. No.:

09/432966

Inventors:

James Vernon Rhodes - Chandler AZ
Robert David Conklin - Chandler AZ
Timothy Allen Barr - Chandler AZ

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1100

US Classification:

714738, 712227

Abstract:

A system for testing IC chips selectively with stored or internally generated bit streams is comprised of a memory which stores instructions of a first class that expressly recite a first bit stream, and stores instructions of a second class that specify operations which generate a second bit stream. A first pattern generator is coupled to the memory, which sequentially reads the instructions of the first and second classes. The first pattern generator includes a time-shared control circuit which sends the first bit stream to a test port on the chips that are tested in response to the first class instructions that are read. In addition, a second pattern generator is coupled to the first pattern generator. This second pattern generator receives the second class instructions that are read; and in response, it sequentially generates portions of the second bit stream by performing the operations which the second class instructions specify. One portion of the second bit stream is sent to the test port on the chips that are tested, while the second pattern generator generates another portion of the second bit stream.

US Patent:

6477676, Nov 5, 2002

Filed:

Nov 3, 1999

Appl. No.:

09/432968

Inventors:

James Vernon Rhodes - Chandler AZ
Robert David Conklin - Chandler AZ

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R 3128

US Classification:

714743, 714723, 711206

Abstract:

An intermediate stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of a plurality of input address registers which hold respective input addresses; and a memory address generator, coupled to the input address registers, which generates a series of memory addresses by selecting bits from the input addresses. A memory is coupled to the memory address generator, which sequentially receives each memory address in the series; and in response, this memory sends a corresponding series of translated addresses to a memory output. Multiple output registers are coupled to the memory output, and each output register stores a respective translated address in the series. With this intermediate stage, the input addresses can be virtual addresses in a virtual, or hypothetical, memory; and, those virtual addresses can be translated into physical addresses for an actual memory chip that is to be tested.

US Patent:

6480981, Nov 12, 2002

Filed:

Nov 3, 1999

Appl. No.:

09/432967

Inventors:

James Vernon Rhodes - Chandler AZ
Robert David Conklin - Chandler AZ

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1100

US Classification:

714738, 341101

Abstract:

An output stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple input registers which hold input addresses and input data words; and a multiplexer circuit, having a plurality of parallel data inputs which concurrently receive the input addresses and the input data words, having control inputs for receiving a sequence of control signals, and which generates serial bit streams by selectively passing bits from the input addresses and input data words in response to the control signals. These serial bit streams from the multiplexer circuit preferably include a first bit stream which defines a data input to an integrated circuit chip that is to be tested, and a second bit stream which defines an expected output from the chip corresponding to the first bit stream. In one particular embodiment, the output stage further includes a memory address generator which generates a sequence of memory addresses, and a memory which receives the sequence of memory addresses, and in response, sends the sequence of control signals from a memory output to the control inputs of the multiplexer circuit. With this embodiment, the memory address generator can include a page register and a counter which together generate the sequence of memory addresses as multiple sub-sequences within respective pages; and the sub-sequences can be generated continuously with no gaps between them so that the serial bit streams from the multiplexer circuit will be generated continuously with no gaps between the serial bits.

US Patent:

6571365, May 27, 2003

Filed:

Nov 3, 1999

Appl. No.:

09/432969

Inventors:

James Vernon Rhodes - Chandler AZ
Robert David Conklin - Chandler AZ

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R 3128

US Classification:

714738, 711206

Abstract:

An initial stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple sets of input registers which store respective addresses; and an address modifying circuit that is coupled to the input registers, which receives commands, and in response, selects one register in one set and generates a modified address by performing arithmetic operations on the address in the selected register. Also, the initial stage includes a boundary check circuit that is coupled to the address modifying circuit, which stores a respective minimum limit and a respective maximum limit for each register set. This initial stage is particularly useful in generating sequences of addresses for memory cells in a chip that is to be tested, where the cells are arranged in rows and columns. When a particular Min/Max limit for a row/column is reached, then that event is remembered by the boundary check circuit. Thereafter, when the next row/column address is generated, the boundary check circuit automatically replaces the generated address (which will exceed the limit) with the proper address.