Jeffrey L Shields

US Patent:

6376877, Apr 23, 2002

Filed:

Feb 24, 2000

Appl. No.:

09/513260

Inventors:

Allen S. Yu - Fremont CA
Jeffrey A. Shields - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257317, 257315, 257321, 257510

Abstract:

A reduced device geometry and increased device efficiency semiconductor memory device is provided. The method of manufacturing the semiconductor memory device includes forming shallow trench isolations (STIs) on the semiconductor substrate, forming a photoresist mask over the STIs, selectively etching the STIs to form curved surface area profiles, growing a layer of tunnel oxide (TOX) over exposed areas of the semiconductor substrate, forming a first polysilicon (poly) layer over the TOX layer and the STIs, chemical-mechanical polishing (CMP) the first poly layer, forming an oxide-nitride-oxide (ONO) layer over the first poly layer, and forming a second poly layer over the ONO layer.

US Patent:

6709924, Mar 23, 2004

Filed:

Nov 12, 2002

Appl. No.:

10/292121

Inventors:

Allen S. Yu - Fremont CA
Jeffrey A. Shields - Sunnyvale CA
Allison Holbrook - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438257, 296359, 296424, 296425, 296426, 296435, 296706, 296725, 438978

Abstract:

For fabricating a shallow trench isolation structure, a notched masking structure is formed over an active area of a semiconductor substrate. A shallow trench opening is formed at a side of the active area with a top corner of the shallow trench opening being exposed and facing a notched surface of the notched masking structure. Liner oxide is formed in a thermal oxidation process at the top corner of the shallow trench opening to round the top corner of the shallow trench opening. The liner oxide may also be formed on walls including the bottom corner of the shallow trench opening during the thermal oxidation process. The shallow trench opening is then filled with a trench dielectric material to form the shallow trench isolation structure.

US Patent:

6774432, Aug 10, 2004

Filed:

Feb 5, 2003

Appl. No.:

10/358589

Inventors:

Minh V. Ngo - Fremont CA
Tazrien Kamal - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Arvind Halliyal - Cupertino CA
Jaeyong Park - Sunnyvale CA
Ning Cheng - Cupertino CA
Jeff P. Erhardt - San Jose CA
Clarence B. Ferguson - San Jose CA
Jeffrey A. Shields - Sunnyvale CA
Angela T. Hui - Fremont CA
Robert A. Huertas - Hollister CA
Tyagamohan Gottipati - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29792

US Classification:

257325, 257324, 257314

Abstract:

A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.

US Patent:

7018896, Mar 28, 2006

Filed:

Apr 5, 2004

Appl. No.:

10/818112

Inventors:

Minh V. Ngo - Fremont CA, US
Tazrien Kamal - San Jose CA, US
Mark T. Ramsbey - Sunnyvale CA, US
Arvind Halliyal - Cupertino CA, US
Jaeyong Park - Sunnyvale CA, US
Ning Cheng - Cupertino CA, US
Jeff P. Erhardt - San Jose CA, US
Clarence B. Ferguson - San Jose CA, US
Jeffrey A. Shields - Sunnyvale CA, US
Angela T. Hui - Fremont CA, US
Robert A. Huertas - Hollister CA, US
Tyagamohan Gottipati - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/00

US Classification:

438261, 438954

Abstract:

A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.

US Patent:

8022468, Sep 20, 2011

Filed:

Mar 29, 2005

Appl. No.:

11/091519

Inventors:

Minh Van Ngo - Fremont CA, US
Wenmei Li - Sunnyvale CA, US
Jeffrey A. Shields - Sunnyvale CA, US
Ning Cheng - San Jose CA, US
Angela Hui - Fremont CA, US
Cinti Xiaohua Chen - Fremont CA, US

Assignee:

Spansion LLC - Sunnyvale CA
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29/66

US Classification:

257325, 257E29309

Abstract:

A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.

US Patent:

20180205012, Jul 19, 2018

Filed:

Jul 20, 2016

Appl. No.:

15/746420

Inventors:

- Santa Clara CA, US
Venkatesh P. Gopinath - Fremont CA, US
Jeffrey Allan Shields - Sunnyvale CA, US
Kuei Chang Tsai - Cupertino CA, US
Chakravarthy Gopalan - Santa Clara CA, US
Michael A. Van Buskirk - Saratoga CA, US

International Classification:

H01L 45/00
H01L 27/24
H01L 23/528
H01L 23/522
G11C 13/00

Abstract:

An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.