Jesse T Jenkins

US Patent:

63169584, Nov 13, 2001

Filed:

May 16, 2000

Appl. No.:

9/573476

Inventors:

Jesse H. Jenkins - Danville CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 40

Abstract:

A programmable logic device including an adjustable length delay line formed by selectively connecting product-term elements in series. Switching circuits connected to the output terminals of each product-term element (e. g. , logic AND gates) that allow the product terms to be routed either to the input terminals of a sum-of-products element (e. g. , a logic OR gate), or to the input terminal of an adjacent product-term element. The length (i. e. , actual signal delay) of the delay line is determined by the number of product-term elements that are connected in series. The output signal from the last product-term element in the series is transmitted through the sum-of-products element. Accordingly, the length of the delay line can be incrementally adjusted by programming the switches to add or subtract product-term elements from the delay line.

US Patent:

61675601, Dec 26, 2000

Filed:

Apr 16, 1998

Appl. No.:

9/061805

Inventors:

Jesse H. Jenkins - Danville CA
Edel M. Young - Palo Alto CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 102

US Classification:

716 17

Abstract:

A method for selecting the state assignments of a complex programmable logic device (CPLD) to minimize power consumption. Within the CPLD, a plurality of macrocells are selected to store a corresponding plurality of state variables, wherein the number of macrocells is selected to be equal to the number of states. For each of the states, one of the macrocells is assigned to store a state variable having a first logic state, and the remaining macrocells are assigned to store state variables having a second logic state. The macrocells storing state variables having the second logic state exhibit a lower power consumption than the macrocell storing the state variable having the first logic state. In addition, each of the macrocells includes a plurality of wired logic gates, each being in a high-current state or a low-current state. The number of wired logic gates in the low-current state is maximized in the macrocells assigned to store the state variables having the second logic state.

US Patent:

55303781, Jun 25, 1996

Filed:

Apr 26, 1995

Appl. No.:

8/430207

Inventors:

Nicholas Kucharewski - Pleasanton CA
David Chiang - Saratoga CA
Jesse H. Jenkins - Danville CA

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41

Abstract:

An erasable programmable logic device (EPLD) includes function blocks connected by a universal interconnect matrix (UIM). The UIM includes both a cross-point circuit and a multiplexer-based (MUX-based) circuit. The cross-point circuit includes intersecting first and second conductors programmably connected by memory cells having control gates connected to the first conductors, drains connected to the second conductors, and sources connected to ground. The MUX-based circuit includes third and fourth conductors programmably connected by pass-gates having first terminals connected to the third conductors, second terminals connected to the fourth conductors, and gates connected to memory cells. The UIM further includes multiple-input multiplexers having first input lines connected to the cross-point circuit, second input lines connected to the MUX-based circuit, and output lines connected to the input lines of the function blocks. The multiple-input multiplexers are programmable to selectively apply signals from either the cross-point circuit or the MUX-based circuit to the function block input lines.

US Patent:

60207574, Feb 1, 2000

Filed:

Mar 24, 1998

Appl. No.:

9/047177

Inventors:

Jesse H. Jenkins - Danville CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 39

Abstract:

A system including a programmable logic device (PLD) mounted on a populated printed circuit board, and a configuration processor. The PLD includes a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer. Each output buffer is coupled to an associated adjustable slew rate control circuit and to an adjustable delay line of the PLD. The configuration processor controls each of the slew rate control circuits to provide a first slew rate. The configuration processor also controls the output buffers to be coupled to the adjustable delay line. The configuration processor then controls the adjustable delay line to generate a first test pulse, which is applied to each of the output buffers. Depending on the impedances of the printed circuit board, the first test pulse transmitted from a particular output buffer may be reflected. Reflected test pulses return to the associated input buffers and are recorded.

US Patent:

61725188, Jan 9, 2001

Filed:

Jul 23, 1999

Appl. No.:

9/360111

Inventors:

Jesse H. Jenkins - Danville CA
Jeffrey H. Seltzer - Los Gatos CA
Derek R. Curd - Fremont CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 738

US Classification:

326 37

Abstract:

A method of minimizing power use in programmable logic devices (PLD) using programmable connections and scrap logic to create a versatile power management scheme. Individual product terms in a PLD can be powered off, thereby saving power, without incurring the power-up and settling time delays seen in the prior art. Power management is not restricted to any one function block, nor must the entire device be powered down, unless so programmed. All conventional logic functionality present in the PLD is available to the power management elements, allowing, in one embodiment, a standard function block to be programmed to operate as the control function block. This logic functionality includes, but is not limited to, internal feedback, combinatorial functions, and register functions. Because scrap logic resources left over from user programming and small programmable connections are used, minimal additional chip surface area is needed. No specific input/output pins are required; in fact, no external connections are required at all, though one or more may be used as inputs to the control function block logic.

US Patent:

57421781, Apr 21, 1998

Filed:

Oct 22, 1996

Appl. No.:

8/740118

Inventors:

Jesse H. Jenkins - Danville CA
Nicholas Kucharewski - Pleasanton CA
David Chiang - Saratoga CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19003

US Classification:

326 33

Abstract:

In a programmable logic device having a plurality of external pins each of which may be driven by an output drive structure controlled by a programmable logic block, a logic device such as an OR gate or a programmable pull-up or pull-down switch is inserted between the input terminal of the output drive structure and the programmable logic block or other internal logic block which controls the output driver. This inserted structure allows the macrocell to be used for internal logic while the output drive structure is used to stabilize power or ground voltage.

US Patent:

61847089, Feb 6, 2001

Filed:

Nov 4, 1999

Appl. No.:

9/434415

Inventors:

Jesse H. Jenkins - Danville CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177
G06F 738

US Classification:

326 39

Abstract:

A system including a programmable logic device (PLD) mounted on a populated printed circuit board, and a configuration processor. The PLD includes a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer. Each output buffer is coupled to an associated adjustable slew rate control circuit and to an adjustable delay line of the PLD. The configuration processor controls each of the slew rate control circuits to provide a first slew rate. The configuration processor also controls the output buffers to be coupled to the adjustable delay line. The configuration processor then controls the adjustable delay line to generate a first test pulse, which is applied to each of the output buffers. Depending on the impedances of the printed circuit board, the first test pulse transmitted from a particular output buffer may be reflected. Reflected test pulses return to the associated input buffers and are recorded.