Jie Yang

US Patent:

6888980, May 3, 2005

Filed:

Dec 9, 2002

Appl. No.:

10/315899

Inventors:

Danny (Dejin) Yu - Fremont CA, US
Li Chen - Fremont CA, US
William (Wei) Yang - Fremont CA, US
Charlie (Shu) Zhang - Fremont CA, US
Jie Yang - Fremont CA, US

Assignee:

BaySpec, Inc. - Fremont CA

International Classification:

G02B006/28
G02B006/32
G02B006/34

US Classification:

385 24, 385 33, 385 37

Abstract:

A device for expanding the wavelength band of an optical component is disclosed. The device has a beam splitter for splitting a wavelength division multiplexed beam into two beams at a desired separation angle. An optical grating separates the two beams into spectral components for each beam. The spectral components are focused on a receiving surface. The separation angle between the two beams expands the wavelength band of the WDM signal.

US Patent:

7149999, Dec 12, 2006

Filed:

Feb 25, 2004

Appl. No.:

10/787070

Inventors:

Andrew B. Kahng - Delmar CA, US
Puneet Gupta - La Jolla CA, US
Dennis Sylvester - Ann Arbor MI, US
Jie Yang - Ann Arbor MI, US

Assignee:

The Regents of the University of California - Oakland CA
The Regents of the University of Michigan - Ann Arbor MI

International Classification:

G06F 17/50

US Classification:

716 19, 716 21

Abstract:

A method for performing a mask design layout resolution enhancement includes determining a level of correction for a mask design layout for a predetermined parametric yield with a minimum total correction cost. The mask design layout is corrected at a determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the mask design layout that are critical for obtaining a desired performance yield are corrected, thereby reducing total cost of correction of the mask design layout.

US Patent:

7313777, Dec 25, 2007

Filed:

Aug 1, 2005

Appl. No.:

11/194357

Inventors:

Jie Yang - Sunnyvale CA, US
Luigi Capodieci - Santa Cruz CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 10, 716 11

Abstract:

Methods and apparatus for checking layouts of circuit features are provided. In one aspect, a method of designing a layout for a circuit feature is provided that includes deriving a function which relates a size and a plurality of aerial image parameters of the circuit feature to a probability of a printing fault in using a lithographic process to pattern the circuit feature. A layout for the circuit feature is created. The function is used to determine a probability of a printing fault in using the lithographic process to pattern the circuit feature and adjust the layout of the circuit feature as necessary in view of the determined probability of printing fault.

US Patent:

7614032, Nov 3, 2009

Filed:

Dec 11, 2006

Appl. No.:

11/637209

Inventors:

Andrew B. Kahng - Delmar CA, US
Puneet Gupta - La Jolla CA, US
Dennis Sylvester - Ann Arbor MI, US
Jie Yang - Ann Arbor MI, US

Assignee:

The Regents of the Univerisity of California - Oakland CA
The Regents of the University of Michigan - Ann Arbor MI

International Classification:

G06F 17/50

US Classification:

716 19, 716 21

Abstract:

A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the design layout that are critical for obtaining the desired performance yield are corrected, thereby reducing the total cost of correction of the design layout.

US Patent:

7757190, Jul 13, 2010

Filed:

Dec 19, 2006

Appl. No.:

11/613006

Inventors:

Vito Dai - Santa Clara CA, US
Jie Yang - Sunnyvale CA, US
Norma Rodriguez - San Jose CA, US
Luigi Capodieci - San Cruz CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 5, 716 4

Abstract:

Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.

US Patent:

7836057, Nov 16, 2010

Filed:

May 23, 2007

Appl. No.:

11/752605

Inventors:

Fadi Victor Micaelian - Belmont CA, US
Richard Sawey - San Carlos CA, US
Emil Mario Scoffone - Menlo Park CA, US
David Brandon Criswell - San Carlos CA, US
Jie Yang - Palo Alto CA, US

Assignee:

Auguri Corporation - San Carlos CA

International Classification:

G06F 7/00
G06F 17/30

US Classification:

707748, 707750

Abstract:

A search engine for databases, data streams, and other data sources allows user preferences as to the relative importance of search criteria to be used to rank the output of the search engine. A weighted preference generator generates weighted preference information including at least a plurality of weights corresponding to a plurality of search criteria. A weighted preference data search engine uses the weighted preference information to search a data source and to provide an ordered result list based upon the weighted preference information. A method for weighted preference data searching further includes allowing a user to re-rank the ordered result list and determine newly updated weighted preferences based on the re-ranking process. A plurality of weights signifying the relative importance of the search criteria may also be generated by the user inputting an ordered list. This ordered list may be a single alternative or a plurality of alternatives.

US Patent:

8088608, Jan 3, 2012

Filed:

Mar 31, 2010

Appl. No.:

12/751985

Inventors:

Jie Yang - Foster City CA, US
Andrew Shaw - Foster City CA, US
Ish Kumar Dhawan - Foster City CA, US
Onorato Campopiano - Hayward CA, US
Kripa Rao - San Mateo CA, US

Assignee:

Codexis, Inc. - Redwood City CA

International Classification:

C12N 9/00

US Classification:

435183

Abstract:

The present invention relates to variant endoglucanases and particularly endoglucanases having improved properties over wild-type endoglucanase.

US Patent:

8103981, Jan 24, 2012

Filed:

Sep 25, 2009

Appl. No.:

12/566925

Inventors:

Andrew B. Kahng - Del Mar CA, US
Puneet Gupta - La Jolla CA, US
Dennis Sylvester - Ann Arbor MI, US
Jie Yang - Ann Arbor MI, US

Assignee:

The Regents of the University of California - Oakland CA
The Regents of the University of Michigan - Ann Arbor MI

International Classification:

G06F 17/50

US Classification:

716 50, 716 51, 716 52, 716 54, 716 55, 716 56

Abstract:

An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield.