Timing recovery circuitry for a digital subscriber line (DSL) modem, including a combined frame and timing function for adjusting frame alignment, and for adjusting sample frequency for frequency offset and for phase offset. Frame alignment is adjusted by averaging estimates of the phase offset over multiple tones within a frame, and then averaging that average estimated phase offset over multiple frames to produce a frame offset measurement. Frequency offset is derived from the constant rate of phase error variation in the received signal varies over a sequence of frames, based on which the sample frequency of the modem is adjusted. Phase offset is determined by averaging the phase offset over a plurality of tones within a frame, and integrating differences in this phase offset from frame to frame.
Jin Lu - Fremont CA, US Po Tong - Los Altos CA, US Chia-Ning Peng - Fremont CA, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03M 13/00
US Classification:
714784, 714761, 714774, 714804
Abstract:
A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a second portion. The processing logic uses the first portion for random error correction and the second portion for erasure error correction.
Systems And Methods For Parameter Modification During Data Processing Retry
Shaohua Yang - Santa Clara CA, US Jin Lu - Lafayette CO, US Haitao Xia - San Jose CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G11B 5/09
US Classification:
360 65, 360 25, 360 31
Abstract:
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: a buffer circuit, an equalizer circuit, a data processing circuit, and a retry determination circuit. The buffer is operable to store digital samples as a buffered output, and the equalizer circuit is operable to equalize the buffered output using a first equalization target to yield a first equalized output, and to yield a second equalized output using a second equalization target. The retry determination circuit is operable to select the second equalization target based at least in part on an occurrence of an error.
Systems And Methods For Data Processing Including Pre-Equalizer Noise Suppression
Shaohua Yang - Santa Clara CA, US Jin Lu - Lafayette CO, US
International Classification:
H04L 27/01
US Classification:
375229
Abstract:
The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.
- Mountain View CA, US Ahmet Onur Tekdas - Santa Clara CA, US Timo Mertens - Millbrae CA, US Okan Kolak - Sunnyvale CA, US Charles Randell Sievert - San Jose CA, US Christine Nguyen - Santa Clara CA, US Jin Lu - Redwood City CA, US
International Classification:
G06F 17/30 H04M 1/725 H04M 1/27 H04W 4/14
Abstract:
The disclosed embodiments include computerized methods, systems, and devices, including computer programs encoded on a computer storage medium, for generating terms of a search query based on a user's spoken utterances, identifying multiple cross-platform messages based on the generated terms, and to generating, via a presentation device, a single interface that enables the user to interact with identified messages. Based on a spoken utterance, the disclosed embodiments may determine user-specified search terms and/or criteria, and based on the user-specified search terms and/or criteria, may obtain cross-platform message data that corresponds to the search query. The communications device may generate one or more interface elements that describe corresponding ones of the cross-platform messages, which may be presented within a unified graphical user interface or voice-user interface by a communications device.
Method And Apparatus For Replication Of Files And File Systems Using A Deduplication Key Space
- Mountain View CA, US Toby Jonathon Coleridge - San Mateo CA, US Pu Paul Zhang - San Jose CA, US Vikram Auradkar - Los Altos CA, US Seshan Parameswaran - Sunnyvale CA, US Kartikeya Iyer - Campbell CA, US Qian Zhang - Sunnyvale CA, US Jin Lu - Sunnyvale CA, US
Assignee:
Atlantis Computing, Inc. - Mountain View CA
International Classification:
G06F 17/30 G06F 9/455
Abstract:
A method and apparatus for rapid replication of deduplicated file system data is described. The method may include initiating replication of a file from a source deduplication system to a destination deduplication system, and transferring deduplication metadata for each block of the file from the source deduplication system to the destination deduplication system. The method may also include transferring an identifier file from the source deduplication system to the destination deduplication system that includes a block number corresponding to a block of the file and a unique identifier value generated from the block of the file. The method may also include receiving a data request file from the destination deduplication system, and transferring the blocks of data identified in the data request file to complete replication of the file on the destination deduplication system.
Name / Title
Company / Classification
Phones & Addresses
Jin Lu President
JINDAI CORPORATION Business Services at Non-Commercial Site · Nonclassifiable Establishments
4793 Lago Vis Cir, San Jose, CA 95129
Jin Lu President
DAILU CORPORATION
1098 Huntingdon Dr, San Jose, CA 95129
Jin Qin Lu President
KAKI TECHNOLOGIES, INC
1707 Clovis Ave, San Jose, CA 95124
Jin Lu President
DL TECHNOLOGIES
7198 Gali Ct #3, San Jose, CA 95129 7198 Galli Ct, San Jose, CA 95129
Exupoli.net
Senior Opto-Mechanical Packaging Engineer
O-Net Dec 2012 - Dec 2013
Senior Photonics and Opto-Mechanical Packaging Engineer
Extreme Ultra Precision Ottawa Laser Jan 2009 - Nov 2013
Senior Mechanical Engineer and Senior Laser Packaging Engineer
Jl Consulting Jlc Aug 2007 - Dec 2008
Senior Photonics Packaging Engineer
Oz Optics Ltd. Jan 2005 - May 2007
Senior Manager In Laser Diode Division
Education:
University of Gent 1989 - 1994
Doctorates, Doctor of Philosophy, Mechatronics Engineering, Philosophy
Central South University 1978 - 1985
Bachelor of Engineering, Bachelors, Mechanical Engineering
Skills:
R&D Fiber Optics Electronics Optics Product Development Precision Mechanical Design Advanced Manufacturing Fea Cad Opto Mechanical Photonics Packaging Manufacturing Engineering Labview Lean Manufacturing Finite Element Analysis Failure Analysis Engineering Management Materials Design For Manufacturing Systems Engineering Testing Process Engineering Solidworks Semiconductors Sensors Spc Materials Science Root Cause Analysis Start Ups