John E Bertsch

US Patent:

6934671, Aug 23, 2005

Filed:

May 29, 2001

Appl. No.:

09/867375

Inventors:

John E. Bertsch - South Hero VT, US
Daniel S. Coops - Burlington VT, US
David M. Fried - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/50
G06F009/45
G06F019/00
G06F017/18
G01R027/28

US Classification:

703 14, 703 13, 703 15, 716 5, 700108, 700109, 700110, 702179, 702182, 702183, 702184, 702185, 702117

Abstract:

A method of performing model to hardware correlation that simulates models based upon design criteria and manufactures devices based upon the design criteria. The method evaluates features of the devices during the manufacturing to produce in-line test parametric data, compares the models to the in-line test parametric data to obtain correlation data, and modifies the simulating according to the correlation data.

US Patent:

54850959, Jan 16, 1996

Filed:

Nov 10, 1994

Appl. No.:

8/337342

Inventors:

John E. Bertsch - Essex VT
Randy W. Mann - Jericho VT
Edward J. Nowak - Essex VT
Minh H. Tong - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3102

US Classification:

324537

Abstract:

Test circuits and methods for accurately flagging out-of-spec resistance in a current carrying structure of an integrated circuit employ a plurality of monitor structures connected in parallel and a test means for monitoring the monitor structures. Each monitor structure includes a test structure and an associated threshold sensitive device. Each test structure is predesigned relative to the current carrying structure of the integrated circuit such that an out-of-spec resistance in the test structure signals a possible out-of-spec resistance in the current carrying structure. The threshold sensitive device of each monitor structure outputs a fail signal when resistance of the associated test structure is above a predefined level. The fail signal is representative of an out-of-spec resistance in the associated test structure and flags possible out-of-spec resistance in the current carrying structure. The test means simultaneously monitors the plurality of monitor structures for a fail signal.

US Patent:

47076674, Nov 17, 1987

Filed:

Apr 30, 1986

Appl. No.:

6/857651

Inventors:

John E. Bertsch - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03F 126

US Classification:

330 9

Abstract:

An amplifier circuit having offset voltage and offset voltage drift corrections which does not require resistive feedback and is suitable for use with unmatched high frequency field effect transistor circuits. The described circuit cancels the offset voltage of a signal amplifier and comprises means for applying differential voltages to an operational amplifier, together with a switchable feedback connecting the output of the amplifier to one of its inputs and a capacitor coupled between the feedback input of the amplifier, and one of the differential voltages. This allows amplifying of low level AC signals while reducing the error introduced by the offset voltage or the offset voltage drift of the amplifier.