John R Mccorkle

US Patent:

6812762, Nov 2, 2004

Filed:

Sep 6, 2002

Appl. No.:

10/235845

Inventors:

Agustin Ochoa - Vista CA
Phuong T. Huynh - Annandale VA
John McCorkle - Vienna VA

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03K 3033

US Classification:

327229, 327401

Abstract:

A mono-cycle generating circuit comprises a control circuit, a multiplexer, and a driver switch circuit. The control circuit generates sets of timing pulses. The multiplexer selects one of the sets of timing pulses. The driver switch circuit outputs a mono-cycle based upon the selected set of timing pulses. The driver switch circuit comprises complementary sets of switches, each complementary set of switches including complementary amplitude pull-up/pull-down functions such that the output mono-cycle is a full rail swing mono-cycle.

US Patent:

7088162, Aug 8, 2006

Filed:

Feb 24, 2005

Appl. No.:

11/063889

Inventors:

Agustin Ochoa - Vista CA, US
Phuong T. Huynh - Annandale VA, US
John McCorkle - Vienna VA, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03K 3/037

US Classification:

327225, 327172, 327176

Abstract:

A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit. The common mode buffer circuit is coupled to the switching circuit and reduces noise generated by the switch circuit.