John C O'Shea

US Patent:

7631128, Dec 8, 2009

Filed:

Jun 28, 2007

Appl. No.:

11/769747

Inventors:

Michael Sgrosso - Franklin MA, US
Jeffrey Kinne - Needham MA, US
Christopher S. MacLellan - Walpole MA, US
John O'Shea - Newton MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 13/42
G06F 3/00
G06F 5/00
G06F 13/12
G06F 13/38
G06F 15/16
G06F 12/00
G06F 13/00

US Classification:

710105, 710 5, 710 36, 710 51, 710 64, 709203, 711130, 711118

Abstract:

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

US Patent:

7987229, Jul 26, 2011

Filed:

Jun 28, 2007

Appl. No.:

11/769744

Inventors:

Jeffrey Kinne - Needham MA, US
John O'Shea - Newton MA, US
Michael Sgrosso - Franklin MA, US
Christopher S. MacLellan - Walpole MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 15/16
G06F 13/00
G06F 13/28

US Classification:

709202, 709200, 711100

Abstract:

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

US Patent:

8090789, Jan 3, 2012

Filed:

Jun 28, 2007

Appl. No.:

11/769745

Inventors:

John O'Shea - Newton MA, US
Jeffrey Kinne - Needham MA, US
Michael Sgrosso - Franklin MA, US
Steven T. McClure - Northboro MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 15/16

US Classification:

709211

Abstract:

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

US Patent:

8156220, Apr 10, 2012

Filed:

Sep 28, 2007

Appl. No.:

11/863530

Inventors:

John O'Shea - Newton MA, US
Jeffrey Kinne - Needham MA, US
Michael Sgrosso - Franklin MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 15/173
G06F 13/00
G06F 11/00

US Classification:

709224, 709223, 709225, 710316, 714 1, 714 18

Abstract:

A method is provided for transmitting user data from a selected one of a plurality of data pipes. The method includes having a ring manager select one of the data pipes from a pool of the data pipes for transmission of the user data. The data is transmitted from the selected one of the data pipes at least one packet switching network. The data pipe detects whether there was an error in the transmission. If there an error detected, the data pipe generates an error interrupt for the ring manager. The ring manager detects the error interrupt and generates an error interrupt for a CPU. The ring manager removes the selected one of the data pipes from the pool of data pipes for a predetermined period of time while the ring manager continues to work on other tasks until the time has expired. During pipe retirement, the physical pipe removed from the pool of pipes is disabled and the router will then direct orphan packets to the error ring. When the time has expired, the ring manager returns the selected data pipe to the pool of available data pipes.

US Patent:

8645623, Feb 4, 2014

Filed:

Jun 28, 2007

Appl. No.:

11/769746

Inventors:

John O'Shea - Newton MA, US
Jeffrey Kinne - Needham MA, US
Michael Sgrosso - Franklin MA, US
Steven T. McClure - Northboro MA, US
Yechiel Yochai - Lincoln RI, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711114, 711100, 711111, 711112, 711147, 711154, 711169

Abstract:

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.