Jonathan D Owen

US Patent:

7607031, Oct 20, 2009

Filed:

Jul 7, 2006

Appl. No.:

11/482269

Inventors:

Paul A. Mackey - Austin TX, US
Paul C. Miranda - Austin TX, US
Larry D. Hewitt - Austin TX, US
Jonathan M. Owen - Northborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713300, 713310, 713323

Abstract:

A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.

US Patent:

7617404, Nov 10, 2009

Filed:

Jul 7, 2006

Appl. No.:

11/482211

Inventors:

Paul A. Mackey - Austin TX, US
Paul C. Miranda - Austin TX, US
Larry D. Hewitt - Austin TX, US
Jonathan M. Owen - Northborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713300, 713320, 713323

Abstract:

A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.

US Patent:

7640315, Dec 29, 2009

Filed:

Aug 4, 2000

Appl. No.:

09/633087

Inventors:

Derrick R. Meyer - Austin TX, US
Jonathan M. Owen - Northboro MA, US
Mark D. Hummel - Franklin MA, US
James B. Keller - Palo Alto CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Alpha Processor, Inc. - Concord MA

International Classification:

G06F 15/16

US Classification:

709210, 709203, 709208, 709209, 709223, 709224, 709225, 709229, 710200

Abstract:

A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. Each unidirectional link forms a point-to-point interconnect to transfer packetized information between two processing nodes. A lock acquisition request from a lock requesting node is placed into service by an arbitrating node when no previous lock requests are pending for service. The arbitrating node transmits a broadcast message to all nodes in the system, which, in turn, respond with a corresponding probe response message to inform the arbitrating node of cessation of issuance of new requests by the node sending the probe response message. The arbitrating node informs the lock requesting node of the requesting node's lock ownership by transmitting a target done message thereto. After completion of lock operations, the lock requesting node sends a lock release request to the arbitrating node, which, in turn, informs all processing nodes of lock release by transmitting another broadcast message within the system.

US Patent:

8583971, Nov 12, 2013

Filed:

Dec 23, 2010

Appl. No.:

12/977338

Inventors:

Sajosh Janarthanam - Austin TX, US
Jonathan Owen - Northborough MA, US
Michael Osborn - Hollis NH, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 29/00

US Classification:

714719, 714801, 714805

Abstract:

A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.

US Patent:

20130227321, Aug 29, 2013

Filed:

Apr 1, 2013

Appl. No.:

13/854616

Inventors:

Norman M. Hack - Pflugerville TX, US
Maurice B. Steinman - Marlborough MA, US
John Kalamatianos - Arlington MA, US
Jonathan M. Owen - Northborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/32

US Classification:

713322, 713323

Abstract:

A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.