Julie Marie Brewer

US Patent:

20210098063, Apr 1, 2021

Filed:

Oct 8, 2020

Appl. No.:

17/066198

Inventors:

- San Jose CA, US
Julie Casperson Brewer - Hoboken NJ, US
Wayne Kinney - Emmett ID, US
Rene Meyer - Fremont CA, US

International Classification:

G11C 13/00
G11C 11/56
H01L 27/24
H01L 45/00

Abstract:

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

US Patent:

20190371396, Dec 5, 2019

Filed:

Jun 3, 2019

Appl. No.:

16/429411

Inventors:

- Sunnyvale CA, US
Julie Casperson Brewer - Hoboken NJ, US
Wayne Kinney - Emmett ID, US
Rene Meyer - Fremont CA, US

International Classification:

G11C 13/00
G11C 11/56
H01L 27/24
H01L 45/00

Abstract:

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

US Patent:

20180114573, Apr 26, 2018

Filed:

Sep 15, 2017

Appl. No.:

15/706356

Inventors:

- Sunnyvale CA, US
Julie Casperson Brewer - Hoboken NJ, US
Wayne Kinney - Emmett ID, US
Rene Meyer - Fremont CA, US

International Classification:

G11C 13/00
H01L 45/00
G11C 11/56
H01L 27/24

Abstract:

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

US Patent:

20160267973, Sep 15, 2016

Filed:

Mar 21, 2016

Appl. No.:

15/075754

Inventors:

- Sunnyvale CA, US
Julie Casperson Brewer - Hoboken NJ, US
Wayne Kinney - Emmett ID, US
Rene Meyer - Fremont CA, US

International Classification:

G11C 13/00
H01L 45/00
H01L 27/24

Abstract:

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

US Patent:

20140367629, Dec 18, 2014

Filed:

Sep 3, 2014

Appl. No.:

14/476604

Inventors:

- Sunnyvale CA, US
Julie Casperson Brewer - Hoboken NJ, US
Wayne Kinney - Emmett ID, US
Rene Meyer - Atherton CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

H01L 45/00
H01L 27/24

US Classification:

257 2

Abstract:

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).