Jun Chen

US Patent:

7188111, Mar 6, 2007

Filed:

Jul 14, 2003

Appl. No.:

10/617826

Inventors:

Jun Chen - Morrisville NC, US
John Goodson - Morrisville NC, US
Peter Coppens - Duffel, BE

Assignee:

Datadirect Technologies Corp. - Bedford MA

International Classification:

G06F 17/30

US Classification:

707 10, 7071041

Abstract:

A system and method for conducting distributed transactions wherein a connect JDBC™ driver for a Microsoft™ SQL Server implements Java™ JTA distributed transactions. To conduct the JTA distributed transactions, JTA specific interfaces are engineered in the driver. The JDBC™ driver is a wire protocol driver in direct TCP communication with the SQL server. During communication, the JDBC™ driver sends packets of information back and forth to and from the database server. These packets may request information form the server, or instruct the server to perform a function, such as executing a stored procedure.

US Patent:

8636911, Jan 28, 2014

Filed:

Oct 7, 2010

Appl. No.:

12/924873

Inventors:

Jun Chen - Fremont CA, US
Guomin Mao - San Jose CA, US
Tom Zhong - Saratoga CA, US
Wei Cao - San Jose CA, US
Yee-Chung Fu - Fremont CA, US

Assignee:

MagIC Technologies, Inc. - Milpitas CA
Advanced Numicro Systems, Inc. - San Jose CA

International Classification:

B81C 1/00

US Classification:

216 2, 216 24, 216 63, 216 66, 216 67, 216 79, 438 29, 438706, 438719

Abstract:

Two methods of fabricating a MEMS scanning mirror having a tunable resonance frequency are described. The resonance frequency of the mirror is set to a particular value by mass removal from the backside of the mirror during fabrication.

US Patent:

20190211476, Jul 11, 2019

Filed:

Sep 25, 2017

Appl. No.:

16/333874

Inventors:

- Stanford CA, US
Peter B. CATRYSSE - Stanford CA, US
Jun CHEN - Stanford CA, US
Shanhui FAN - Stanford CA, US
Po-Chun HSU - Stanford CA, US
Yucan PENG - Stanford CA, US
Alex Yu SONG - Stanford CA, US

International Classification:

D01F 6/04
A41D 31/04
D01F 6/46
D03D 15/00
D01F 1/10
D01F 6/06
D03D 1/00

Abstract:

A fiber includes an elongated member and refractive index contrast domains dispersed within the elongated member. The elongated member includes at least one polymer having a transmittance of infrared radiation at a wavelength of 9.5μπι of at least about 40%.

US Patent:

20180129772, May 10, 2018

Filed:

Jul 19, 2017

Appl. No.:

15/654565

Inventors:

- Mountain View CA, US
Jun Chen - Cary NC, US
Gary B. Nifong - Durham NC, US

International Classification:

G06F 17/50

Abstract:

Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions.

US Patent:

20150339426, Nov 26, 2015

Filed:

May 15, 2015

Appl. No.:

14/713488

Inventors:

- Mountain View CA, US
Jun Chen - Cary NC, US
Karthikeyan Muthalagu - Morrisville NC, US
James Lewis Nance - Raleigh NC, US

International Classification:

G06F 17/50

Abstract:

A virtual hierarchical layer (VHL) is constructed for a semiconductor design in order to reduce the computational requirement of design rules checking (DRC) and design rules for manufacture (DRM) procedures. In order to form the VHL, a negative plane is created. A cell and multiple instances of the cell are then identified in the semiconductor design and polygons which overlap the cell and its instances are determined. The polygons are pushed into the negative plane to create holes in the plane. Shapes overlapping other instances of the cell which fall onto holes in the solid virtual cell plane are ignored. The resulting holed solid virtual cell plane can then be inverted to create a VHL to be used for design simulation and verification.

US Patent:

20150339430, Nov 26, 2015

Filed:

Feb 27, 2015

Appl. No.:

14/634695

Inventors:

- Mountain View CA, US
Jun Chen - Cary NC, US
James Lewis Nance - Raleigh NC, US
Zhen Ren - Morrisville NC, US
Ying Shi - Chapel Hill NC, US

International Classification:

G06F 17/50

Abstract:

Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes.

US Patent:

20150339432, Nov 26, 2015

Filed:

Mar 30, 2015

Appl. No.:

14/673709

Inventors:

- Mountain View CA, US
Jun Chen - Cary NC, US
Gary B. Nifong - Durham NC, US

International Classification:

G06F 17/50

Abstract:

Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions.

US Patent:

20150339433, Nov 26, 2015

Filed:

May 15, 2015

Appl. No.:

14/713716

Inventors:

- Mountain View CA, US
Jun Chen - Cary NC, US
Karthikeyan Muthalagu - Morrisville NC, US
James Lewis Nance - Raleigh NC, US
Zhen Ren - Morrisville NC, US
Ying Shi - Chapel Hill NC, US

International Classification:

G06F 17/50

Abstract:

Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.