Jung Soon Cho

US Patent:

20130042135, Feb 14, 2013

Filed:

Aug 12, 2011

Appl. No.:

13/208669

Inventors:

Herbert Lopez-Aguado - Sunnyvale CA, US
Jung Wook Cho - Cupertino CA, US
Conrad H. Ziesler - Seattle WA, US

International Classification:

G06F 1/12

US Classification:

713400

Abstract:

A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.

US Patent:

20230109984, Apr 13, 2023

Filed:

Jan 11, 2022

Appl. No.:

17/573274

Inventors:

- Cupertino CA, US
Inder M. Sodhi - Palo Alto CA, US
Keith Cox - Sunnyvale CA, US
Jung Wook Cho - Cupertino CA, US
Kevin I. Park - San Francisco CA, US
Tal Kuzi - Tel Aviv, IL

International Classification:

G06F 1/3234
G06F 1/3206

Abstract:

In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

US Patent:

20230101217, Mar 30, 2023

Filed:

Jan 11, 2022

Appl. No.:

17/573268

Inventors:

- Cupertino CA, US
Inder M. Sodhi - Palo Alto CA, US
Keith Cox - Sunnyvale CA, US
Jung Wook Cho - Cupertino CA, US
Kevin I. Park - San Francisco CA, US
Tal Kuzi - Tel Aviv, IL

International Classification:

G06F 1/3296
G06F 1/324
G06F 1/3234

Abstract:

In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

US Patent:

20160291625, Oct 6, 2016

Filed:

Mar 30, 2015

Appl. No.:

14/673326

Inventors:

- Cupertino CA, US
Eric G. Smith - Palo Alto CA, US
Erik P. Machnicki - San Jose CA, US
Jung Wook Cho - Cupertino CA, US
Khaled M. Alashmouny - Santa Clara CA, US
Kiran B. Kattel - San Francisco CA, US
Vijay M. Bettada - Fremont CA, US
Bo Yang - Santa Clara CA, US
Wenlong Wei - San Jose CA, US

International Classification:

G05F 3/02

Abstract:

An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.