Kai H Cheng

US Patent:

7093079, Aug 15, 2006

Filed:

Dec 17, 2002

Appl. No.:

10/323200

Inventors:

Tuan M. Quach - Fullerton CA, US
Lily Pao Looi - Portland OR, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711141, 711146, 711137

Abstract:

Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.

US Patent:

7617329, Nov 10, 2009

Filed:

Dec 30, 2002

Appl. No.:

10/335001

Inventors:

Tuan M. Quach - Fullerton CA, US
Lily P. Looi - Portland OR, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/16

US Classification:

709253, 709230, 711118, 711131, 711140, 711141, 711146

Abstract:

A system includes a scalability port switch (SPS) and a plurality of nodes. The SPS has a plurality of ports, each port coupled to a node. Each port is connected to a scalability port protocol distributed (SPPD). A snoop filter in the SPS tracks which nodes may be using various memory addresses. A scalability port protocol central (SPPC) is responsible for processing messages to support coherent and non-coherent transactions in the system.

US Patent:

20150058524, Feb 26, 2015

Filed:

Jan 4, 2012

Appl. No.:

13/808314

Inventors:

Kenneth C. Creta - Gig Harbor WA, US
Jason W. Horihan - Hillsboro WA, US
Robert G. Blankenship - Tacoma WA, US
Kai Cheng - Portland OR, US

International Classification:

G06F 3/06
G11C 13/00
G11C 14/00

US Classification:

711103, 711147

Abstract:

Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed.

US Patent:

20140129767, May 8, 2014

Filed:

Sep 30, 2011

Appl. No.:

13/997189

Inventors:

Raj K Ramanujan - Federal Way WA, US
Rajat Agarwal - Beaverton OR, US
Kai Cheng - Portland OR, US
Taarinya Polepeddi - London, GB
Camille C. Raad - Folsom CA, US
David J. Zimmerman - El Dorado Hills CA, US
Muthukumar P. Swaminathan - Folsom CA, US
Dimitrios Ziakas - Hillsboro OR, US
Mohan J. Kumar - Aloha OR, US
Bassam N. Coury - Dupont WA, US
Glenn N. Hinton - Portland OR, US

International Classification:

G06F 12/08
G11C 14/00
G11C 11/406

US Classification:

711105, 711122

Abstract:

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”