Kenneth Lane Bean

US Patent:

45992479, Jul 8, 1986

Filed:

Jan 4, 1985

Appl. No.:

6/688771

Inventors:

Kenneth E. Bean - Richardson TX
Robert H. Havemann - Garland TX
Andrew Lane - Westminster TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B05D 512
C23C 1600

US Classification:

427 93

Abstract:

The disclosure relates to a method of growing thermal oxide on silicon wherein the oxide is grown at an increased rate, at reduced temperature or a combination thereof. This is accomplished by operating in an hermetic quartz tube capable of withstanding high pressure with steam or oxygen at super atmospheric pressure.

US Patent:

39697495, Jul 13, 1976

Filed:

May 19, 1975

Appl. No.:

5/578451

Inventors:

Kenneth E. Bean - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2704
H01L 2712

US Classification:

357 49

Abstract:

Process permitting control of the thickness of the thin layer of semiconductor material by first forming a slot of a predetermined depth in one surface so that the slot will be exposed during removal of material from the opposite surface should the thickness of the thin layer of semiconductor material become less than the depth of the slot, and a (110) oriented semiconductor substrate having a slot formed therein which is bounded by converging {111} planes. In a preferred embodiment the thickness control is realized by first preparing the slice of semiconductor material so that at least one of its surfaces has a (100) orientation. There is then formed on the surface of the slice having the (100) orientation an etch-resistant mask having a window opened therethrough such that the window defines on the surface of the slice two lines which are parallel to each other and to lines defined by the intersection of {111} planes with the surface of the slice. Semiconductor material is then removed through the windows by etching to produce a slot having a depth greater than thickness to which the single crystal semiconductor material is to be subsequently processed. A vapor deposited support layer may then be produced on the surface of the slice to which the mask was attached during which process it will fill the slot etched in the semiconductor material through the window.

US Patent:

46636480, May 5, 1987

Filed:

Dec 19, 1984

Appl. No.:

6/684197

Inventors:

Kenneth E. Bean - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2142
H01L 21461
H01L 2904

US Classification:

357 55

Abstract:

The disclosure relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.

US Patent:

39697460, Jul 13, 1976

Filed:

Dec 10, 1973

Appl. No.:

5/423630

Inventors:

Don Leslie Kendall - Richardson TX
Francois Antoine Padovani - Dallas TX
Kenneth Elwood Bean - Richardson TX
Walter Theodore Matzen - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2904
H01L 3106
H01L 2120
H01L 21308

US Classification:

357 30

Abstract:

Disclosed is a method of fabricating a vertical multi-junction cell and the solar cell produced thereby, utilizing an orientation dependent etch to selectively provide parallel grooves in monocrystalline silicon body, followed by the introduction of doping impurities of the opposite conductivity type from the silicon body to provide PN junctions. In some instances the grooves are filled with silicon of the same conductivity type as the silicon body.

US Patent:

39899462, Nov 2, 1976

Filed:

Mar 31, 1975

Appl. No.:

5/563541

Inventors:

Richard A. Chapman - Dallas TX
Kenneth E. Bean - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01J 3149

US Classification:

250332

Abstract:

This disclosure defines an infrared image detector formed in a block of semiconductor material by etching slots in the semiconductor material. The slots define the individual detectors, effectively isolate them from each other both optically and electrically, and permit the detectors to be placed very close to each other.

US Patent:

47374705, Apr 12, 1988

Filed:

Sep 12, 1986

Appl. No.:

6/907184

Inventors:

Kenneth E. Bean - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21302

US Classification:

437 38

Abstract:

The disclosure relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.

US Patent:

40509796, Sep 27, 1977

Filed:

Jan 14, 1976

Appl. No.:

5/649130

Inventors:

Ronald K. Smeltzer - Dallas TX
Kenneth E. Bean - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21306

US Classification:

156647

Abstract:

This disclosure relates to methods of producing thin layers of silicon as well as thin layers of silicon on insulating substrates such as silicon dioxide or polycrystalline silicon by forming either an n- layer of single crystal silicon over a p++ layer of single crystal silicon or a p- layer of single crystal silicon over an n++ layer of single crystal silicon and then removing either the n++ or p++ single crystal substrate, as the case may be, by utilizing an etch which will only etch the n++ or p++ region and will stop when the n- or p- region, as the case may be, has been reached.

US Patent:

52504450, Oct 5, 1993

Filed:

Jan 17, 1992

Appl. No.:

7/824770

Inventors:

Kenneth E. Bean - Richardson TX
Satwinder S. Malhi - Garland TX
Walter R. Runyan - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21205

US Classification:

437 11

Abstract:

A semiconductor wafer (32) is patterned to have gettering areas (36-38) selectively positioned proximate devices (44-46) which require gettering. The areas (36-38) comprise germanium-doped silicon having a germanium concentration of approximately 1. 5%-2. 0%. The germanium creates a lattice mismatch between the substrate (32) and an epitaxial layer (34) which is sufficient to produce defects capable of gettering contaminants. The gettering areas (36-38) may be formed by selective deposition, selective etching, ion-implantation or selective diffusion techniques.