Lindsey R Hall

US Patent:

6448182, Sep 10, 2002

Filed:

Nov 22, 1999

Appl. No.:

09/447172

Inventors:

Lindsey Hall - Dallas TX
Jennifer Sees - The Colony TX
Ashutosh Misra - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21302

US Classification:

438692, 438693, 252 791

Abstract:

An embodiment of the instant invention is a method of fabricating an electrical device having a structure overlying a semiconductor substrate which is planarized using chemical mechanical planarization, the method comprising the steps of: forming a layer of material over the semiconductor wafer; polishing the layer of material by subjecting it to a polishing pad and a slurry which includes peroxygen; and wherein the slurry additionally includes a stabilizing agent which retards the decomposition of the peroxygen in the slurry. Preferably, the stabilizing agent is comprised of: pyrophosphoric acids, polyphosphonic acids, polyphosphoric acids, Ethylenediamine Tetraacetic acid, a salt of the pyrophosphoric acids, a salt of the polyphosphonic acids, a salt of the polyphosphoric acids, a salt of the Ethylenediamine Tetraacetic acid and any combination thereof. In addition, the stabilizing agent may be comprised of: sodium pyrophosphate decahydrate, sodium pyrophosphate decahydrate, and/or 8-hydroxyquinoline. The decomposition of the peroxygen in the slurry is catalyzed by transition metals included in the slurry, and may be caused by the pH of the slurry.

US Patent:

6656748, Dec 2, 2003

Filed:

Apr 18, 2002

Appl. No.:

10/125662

Inventors:

Lindsey H. Hall - Plano TX
Scott R. Summerfelt - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2100

US Classification:

438 3, 438 4, 438240

Abstract:

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a âshorting outâ of the resulting FeRAM capacitor.

US Patent:

6876021, Apr 5, 2005

Filed:

Nov 25, 2002

Appl. No.:

10/303560

Inventors:

J. Scott Martin - Garland TX, US
Scott R. Summerfelt - Garland TX, US
Theodore S. Moise - Dallas TX, US
Kelly J. Taylor - Allen TX, US
Luigi Colombo - Dallas TX, US
Sanjeev Aggarwal - Plano TX, US
Sirisha Kuchimanchi - Dallas TX, US
K. R. Udayakumar - Dallas TX, US
Lindsey Hall - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L031/119

US Classification:

257295, 257296

Abstract:

The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.

US Patent:

6995088, Feb 7, 2006

Filed:

May 18, 2004

Appl. No.:

10/848219

Inventors:

Sanjeev Aggarwal - Plano TX, US
Lindsey Hall - Plano TX, US
Trace Q. Hurd - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44

US Classification:

438687, 438679

Abstract:

The present invention provides, in one embodiment, a method of forming a copper layer () over a semiconductor substrate (). The method comprises coating a copper seed layer () located over a semiconductor substrate with a protective agent () to form a protective layer (). The method also includes placing the semiconductor substrate in an acid bath () to remove the protective layer. The method further includes electrochemically depositing a second copper layer () on the copper seed layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

US Patent:

7060579, Jun 13, 2006

Filed:

Jul 29, 2004

Appl. No.:

10/902360

Inventors:

PR Chidambaram - Richardson TX, US
Lindsey Hall - Plano TX, US
Haowen Bu - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336
H01L 21/76
H01L 21/3205
H01L 21/4763

US Classification:

438303, 438297, 438439, 438589

Abstract:

A method () of forming a transistor includes forming a gate structure () over a semiconductor body and forming recesses () using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body toward a channel portion of the semiconductor body underlying the gate structure. The method further includes epitaxially growing silicon () comprising stress-inducing species in the recesses. The source and drain regions are then implanted () in the semiconductor body on opposing sides of the gate structure.

US Patent:

7153706, Dec 26, 2006

Filed:

Apr 21, 2004

Appl. No.:

10/829053

Inventors:

Sanjeev Aggarwal - Plano TX, US
Kelly J. Taylor - Allen TX, US
Lindsey Hall - Plano TX, US
Satyavolu Srinivas Papa Rao - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/00

US Classification:

438 3, 438240, 438633

Abstract:

The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (), among other elements, includes a substantially planar ferroelectric dielectric layer () located over a first electrode layer (), wherein the substantially planar ferroelectric dielectric layer () has an average surface roughness of less than about nm. The ferroelectric capacitor () further includes a second electrode layer () located over the substantially planar ferroelectric dielectric layer ().

US Patent:

7217626, May 15, 2007

Filed:

Jul 26, 2004

Appl. No.:

10/899360

Inventors:

Haowen Bu - Plano TX, US
PR Chidambaram - Richardson TX, US
Rajesh Khamankar - Coppell TX, US
Lindsey Hall - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336

US Classification:

438303, 438184

Abstract:

Methods () are presented for transistor fabrication, in which first and second sidewall spacers () are formed laterally outward from a gate structure (), after which a source/drain region () is implanted. The method () further comprises removing all or a portion of the second sidewall spacer () after implanting the source/drain region (), where the remaining sidewall spacer () is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

US Patent:

7220600, May 22, 2007

Filed:

Dec 17, 2004

Appl. No.:

11/016400

Inventors:

Scott R. Summerfelt - Dallas TX, US
Lindsey H. Hall - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01G 7/06
H01L 32/00

US Classification:

438 3, 438689, 438240

Abstract:

Methods () are provided for fabricating a ferroelectric capacitor structure including methods () for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching () portions of an upper electrode, etching () ferroelectric material, and etching () a lower electrode to define a patterned ferroelectric capacitor structure, and etching () a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing () the patterned ferroelectric capacitor structure using a first ashing process, performing () a wet clean process after the first ashing process, and ashing () the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.