Mark Robert French

US Patent:

7519797, Apr 14, 2009

Filed:

Nov 2, 2006

Appl. No.:

11/556020

Inventors:

Gregory J. Stiehl - Austin TX, US
David L. Anderson - Durham NC, US
Cass W. Everitt - Round Rock TX, US
Mark J. French - Raleigh NC, US
Steven E. Molnar - Chapel Hill NC, US

Assignee:

NIVIDIA Corporation - Santa Clara CA

International Classification:

G06F 9/00
G06F 15/76

US Classification:

712227, 712 4, 712225

Abstract:

An event occurring in a graphics pipeline is detected and counted at the location of its occurrence using an event detector and a local counter. The event count maintained by the local counter is reported asynchronously to a global counter. The global counter is configured to be of higher precision than the local counter and is positioned at a place that is convenient for reporting the events, e. g. , at the end of the graphics pipeline.

US Patent:

7616209, Nov 10, 2009

Filed:

Jun 16, 2006

Appl. No.:

11/454230

Inventors:

Steven E. Molnar - Chapel Hill NC, US
Mark J. French - Raleigh NC, US
Cass W. Everitt - Round Rock TX, US
Adam Clark Weitkemper - Morrisville NC, US
Phillip Keslin - San Jose CA, US
David L. Anderson - Durham NC, US
George R. Lynch - Raleigh NC, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/36
G06F 13/00
G06F 13/28

US Classification:

345545, 345557, 711137

Abstract:

Prescient cache management methods and systems are disclosed. In one embodiment, within a pre-raster engine operations stage in a graphics rendering pipeline, tile entries are stored in a buffer. Each of these tile entries is related a transaction request that enters the pre-raster engine operations stage and has a screen coordinates field and a conflict field. If this buffer includes a first tile entry, which is related to a first transaction request associated with a first tile, and a second tile entry, which is related to a second transaction request that enters the pre-raster engine operations stage after the first transaction request and is also associated with the first tile, the conflict field of the first tile entry is updated with a conflict type that reflects a number of tile entries between the first tile entry and the second tile entry.

US Patent:

7620798, Nov 17, 2009

Filed:

Oct 30, 2006

Appl. No.:

11/554511

Inventors:

Mark J. French - Raleigh NC, US
Steven E. Molnar - Chapel Hill NC, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 9/38

US Classification:

712216, 712200, 712228

Abstract:

A synchronization mechanism is used to synchronize events across multiple execution pipelines that process transaction streams. A common set of state configuration is included in each transaction stream to control processing of data that is distributed between the different transaction streams. Portions of the state configuration correspond to portions of the data. Execution of the transaction streams is synchronized to ensure that each portion of the data is processed using the state configuration that corresponds to that portion of the data. The synchronization mechanism may be used for multiple synchronizations and when the synchronization signals are pipelined to meet chip-level timing requirements.

US Patent:

7626588, Dec 1, 2009

Filed:

Jun 16, 2006

Appl. No.:

11/454225

Inventors:

Steven E. Molnar - Chapel Hill NC, US
Mark J. French - Raleigh NC, US
Cass W. Everitt - Round Rock TX, US
Adam Clark Weitkemper - Morrisville NC, US
Phillip Keslin - San Jose CA, US
David L. Anderson - Durham NC, US
George R. Lynch - Raleigh NC, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/36
G06F 12/00

US Classification:

345557, 711137

Abstract:

Prescient cache management methods and systems are disclosed. In one embodiment, a local cache that operates within a raster engine operations stage of a graphics rendering pipeline is managed by following a number of caching decisions related to a number of cached tiles. Each of these cached tiles has a certain priority to remain in the local cache, with the priority corresponding to a conflict type received from a buffer operating within a pre-raster engine operations stage of the graphics rendering pipeline.

US Patent:

7692659, Apr 6, 2010

Filed:

Nov 6, 2006

Appl. No.:

11/557076

Inventors:

Steven E Molnar - Chapel Hill NC, US
Daniel P. Wilde - Cedar Park TX, US
Mark J. French - Raleigh NC, US
Robert J. Stoll - Los Altos CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/60
G09G 5/36
G06T 9/00
G09G 5/02
G06K 9/00
G06K 9/40
G06K 9/54

US Classification:

345501, 345426, 345549, 345555, 345589, 382162, 382166, 382254, 382305

Abstract:

One embodiment of the present invention sets forth a technique for improving graphics rendering efficiency by processing pixels in a compressed format whenever possible within a multi-sampling graphics pipeline. Each geometric primitive is rasterized into fragments, corresponding to screen space pixels covered at least partially by the geometric primitive. Fragment coverage represents the pixel area covered by the geometric primitive and determines the weighted contribution of a fragment color to the corresponding screen space pixel. Samples associated with a given fragment are called sibling samples and have the same color value. The property of sibling samples having the same color value is exploited to compress and process multiple samples, thereby reducing the size of the associated logic and the amount of data written to and read from the frame buffer.

US Patent:

7768519, Aug 3, 2010

Filed:

Sep 19, 2006

Appl. No.:

11/533293

Inventors:

David L. Anderson - Durham NC, US
Mark J. French - Raleigh NC, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/80
G06F 13/00
G06F 9/46

US Classification:

345505, 345537, 718105

Abstract:

A high-performance crossbar for a pipeline is disclosed. In particular, one embodiment of the crossbar receives multimedia data at a first throughput from a source operating in a first pipeline stage. The received data are stored in at least one input buffer corresponding to the source in the crossbar. The crossbar also causes the multimedia data from the input buffer to be routed to at least one output buffer at a second throughput. The output buffer corresponds to a destination operating in a second pipeline stage. Then the crossbar causes the multimedia data from the output buffer to be routed to the destination at the first throughput.

US Patent:

7830392, Nov 9, 2010

Filed:

Dec 18, 2006

Appl. No.:

11/612415

Inventors:

John M. Danskin - Providence RI, US
Steven E. Molnar - Chapel Hill NC, US
John S. Montrym - Los Altos Hills CA, US
Mark French - Raleigh NC, US
John H. Edmondson - Arlington MA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/02
G06F 15/80
G06F 15/50
G09G 5/00

US Classification:

345544, 345426, 345505, 345612

Abstract:

The number of crossbars in a graphics processing unit is reduced by assigning each of a plurality of pixels to one of a plurality of pixel shaders based at least in part on a location of each of the plurality of pixels within an image area, generating an attribute value for each of the plurality of pixels using the plurality of pixel shaders, mapping the attribute value of each of the plurality of pixels to one of a plurality of memory partitions, and storing the attribute values in the memory partitions according to the mapping. The attribute value generated by a particular one of the pixel shaders is mapped to the same one of the plurality of memory partitions.

US Patent:

7880747, Feb 1, 2011

Filed:

Dec 13, 2006

Appl. No.:

11/610127

Inventors:

Steven E. Molnar - Chapel Hill NC, US
Henry P. Moreton - Woodside CA, US
Daniel P. Wilde - Cedar Park TX, US
Mark J. French - Raleigh NC, US
Bengt-Olaf Schneider - Yorktown Heights NY, US
Jonathan J. Dunaisky - Fort Collins CO, US
Weizhong Xu - Fremont CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/02

US Classification:

345592, 345589, 345600, 345614, 345506, 345556, 712233, 712234

Abstract:

A technique for handling floating-point special values, e. g. , Infinity, NaN, −Zero, and denorms, during blend operations is provided so that blend operations on fragment color values that contain special values can be performed in compliance with special value handling rules. In particular, the presence of special values is detected or the potential presence of special values is detected. This information is used to qualify when blend optimizations may be performed, so that floating point blend operations can remain conformant to special value handling rules.