Mark A Hawes

US Patent:

7512507, Mar 31, 2009

Filed:

Mar 23, 2006

Appl. No.:

11/277338

Inventors:

Scott N. Gatzemeier - Boise ID, US
Joemar D. Sinipete - Boise ID, US
Robert J. Ringhofer - Boise ID, US
Nevil Gajera - Boise ID, US
Mark A. Hawes - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 27/28

US Classification:

702117

Abstract:

Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the individual die are more finely tuned and more die operate at the target specifications so that yield is increased. In an embodiment, the odd and even blocks of each non volatile memory die are erased and then programmed to test the program time. Statistical analysis of the tested program times is performed. Based on this analysis the trim values are determined and programmed into the die. Accordingly, each die on a wafer has its individual trim settings.

US Patent:

7567472, Jul 28, 2009

Filed:

Apr 12, 2006

Appl. No.:

11/402534

Inventors:

Scott N. Gatzemeier - Boise ID, US
Joemar Sinipete - Boise ID, US
Nevil Gajera - Boise ID, US
Mark Hawes - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 29/00

US Classification:

365201

Abstract:

A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is less than or equal to a first predetermined time, and failing the memory block if the total programming time for the memory block exceeds the first predetermined time or the programming time for any one of the pages exceeds a second predetermined time.

US Patent:

8094508, Jan 10, 2012

Filed:

Jul 27, 2009

Appl. No.:

12/509739

Inventors:

Scott N. Gatzemeier - Boise ID, US
Joemar Sinipete - Boise ID, US
Nevil Gajera - Boise ID, US
Mark Hawes - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

365201

Abstract:

A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number.

US Patent:

20130272071, Oct 17, 2013

Filed:

Apr 11, 2012

Appl. No.:

13/444443

Inventors:

Violante Moschiano - Bacoli, IT
Tommaso Vali - Sezze, IT
Mark A. Hawes - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G11C 16/10
G11C 16/04

US Classification:

36518524, 36518518

Abstract:

The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.

US Patent:

53312279, Jul 19, 1994

Filed:

Dec 13, 1993

Appl. No.:

8/166662

Inventors:

Mark A. Hawes - Boise ID

Assignee:

Micron Semiconductor, Inc. - Boise ID

International Classification:

H03K 19173

US Classification:

307465

Abstract:

A programmable logic device (PLD) output macrocell circuit is disclosed. Specifically, there is a macrocell having an exclusive logic signal feedback line and an exclusive external input signal line both feeding into the input of the PLD.

US Patent:

53845005, Jan 24, 1995

Filed:

Dec 22, 1993

Appl. No.:

8/171865

Inventors:

Mark A. Hawes - Boise ID
Paul S. Zagar - Boise ID

Assignee:

Micron Semiconductor, Inc. - Boise ID

International Classification:

H03K 19173

US Classification:

326 39

Abstract:

A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a macrocell having an exclusive logic signal feedback line and an exclusive external input signal line both feeding into the input of the PLD. Exactly, this PLD can disable the I/O pad and still have an internal feedback to its logic circuitry.

US Patent:

50862901, Feb 4, 1992

Filed:

Mar 8, 1990

Appl. No.:

7/490282

Inventors:

Shawn G. Murray - Portland OR
Mark A. Hawes - Beaverton OR

International Classification:

G08B 108
H04Q 700

US Classification:

340539

Abstract:

A mobile perimeter monitoring system includes a battery powder transmitter adapted to be placed upon the person to be monitored while the system user carries a receiver. The receiver responds to a code transmitted by the transmitter and provides an in-range or out-of-range indication depending upon whether the receiver is within the effective range of the transmitter or outside of its effective range. An adjustment on the receiver allows the user to adjust the effective range of the system for varying environments. The receiver may be operated in an in-range mode or an out-of-range mode to provide both perimeter monitoring capability and the ability to track a transmitter if its moves outside the perimeter.

US Patent:

60165618, Jan 18, 2000

Filed:

Jun 18, 1998

Appl. No.:

9/099831

Inventors:

Fariborz F. Roohparvar - Cupertino CA
Allahyar Vahidi Mowlavi - Santa Clara CA
Mark A. Hawes - Boise ID
Gregory L. Cowan - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 3128

US Classification:

714720

Abstract:

A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different. An output circuit, coupled to the first and second detection circuits, generates y number of output data bits which are arranged in a pattern indicative of whether the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are identical, are arranged in a pattern in which each two adjacent bits are different, or are arranged in another pattern, and wherein y is less than x. A method of testing an integrated circuit (IC) memory is also disclosed.

Address:

3486 N Columbine Ave, Boise, ID 83713

Phone:

(208)3771848

VIN:

2GCEK13Z171164467

Make:

CHEVROLET

Model:

SILVERADO 1500 CLASSIC

Year:

2007