Mark W Mcdermott

US Patent:

51577810, Oct 20, 1992

Filed:

Jan 2, 1990

Appl. No.:

7/459484

Inventors:

Wallace B. Harwood - Austin TX
Mark W. McDermott - Austin TX
Dennis K. Verbeek - Round Rock TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 100

US Classification:

395575

Abstract:

A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register is placed in predetermined circuit portions which each can then operate in a normal mode and a test mode. A central processing unit (CPU) may initiate a test operation in any of the circuit portions in response to software executing by writing an operand to a centralized test module. Operands are scanned into and out of a circuit portion being tested while the central processing unit is capable of performing non-test processing activites. The CPU may also test itself using a dedicated test register which can only cause the CPU to enter a test mode after the register is written to.

US Patent:

43665608, Dec 28, 1982

Filed:

Sep 22, 1980

Appl. No.:

6/189974

Inventors:

Mark W. McDermott - Austin TX
Neil B. Feldman - Manchaca TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H02H 324
G08B 2100
H03K 500
H03K 326

US Classification:

365228

Abstract:

A circuit for detecting power supply variations in which a first and second transistor are connected in a cross-coupled mode. A load device is connected to each transistor and to a source of power. The loads are unbalanced such that upon application of power to the circuit a first state is always assumed. The cell is forced to its second state. A charge transfer device is connected between first and second nodes formed at the connection between the first transistor and its load and the second transistor and its load. Upon reduction of power supply voltage below that of the active node, a charge transfer takes place which allows the cell to return to its initial state. Detection of the initial state indicates loss or reduction of power has occurred.

US Patent:

53613929, Nov 1, 1994

Filed:

Mar 19, 1993

Appl. No.:

8/033992

Inventors:

Antone L. Fourcroy - Austin TX
Mark W. McDermott - Austin TX
John P. Dunn - Austin TX
Bradley G. Burgess - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 930
G06F 946
G06F 1324
G06F 1120

US Classification:

395800

Abstract:

A digital computing system having a low power mode of operation includes a mechanism for communicating, prior to entering the low power mode, information determinative of which events shall be capable of causing the termination of the low power mode. An integrated circuit microcomputer enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system within the microcomputer. This subsystem then shuts down the clock signals to the remainder of the microcomputer, leaving only this sub-system active. The active sub-system performs a comparison of the priority levels of received interrupt requests to the interrupt mask during the low power mode.

US Patent:

55921078, Jan 7, 1997

Filed:

Jun 30, 1995

Appl. No.:

8/497491

Inventors:

Mark W. McDermott - Austin TX
John E. Turner - Austin TX

Assignee:

Cyrix Corporation - Richardson TX

International Classification:

H03K 190948

US Classification:

326 49

Abstract:

A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). C inputs control p- and n-channel transistors. Depending on whether the C input is deasserted or asserted, respective internal nodes are shorted to effect the selected configuration. Specifically, deasserting C provides the NAND configuration, while asserting C provides the NOR configuration. In an alternative embodiment, the NAND/NOR logic element can be used in a full adder to provide the carry output.

US Patent:

55680674, Oct 22, 1996

Filed:

Jun 30, 1995

Appl. No.:

8/497007

Inventors:

Mark W. McDermott - Austin TX
John E. Turner - Austin TX

Assignee:

Cyrix Corporation - Richardson TX

International Classification:

H03K 19094
H03K 1921

US Classification:

326 55

Abstract:

A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration. In an alternative embodiment, the XNOR/XOR logic element can be used in a full adder to provide the sum output.

US Patent:

59260530, Jul 20, 1999

Filed:

Dec 15, 1995

Appl. No.:

8/572813

Inventors:

Mark W. McDermott - Austin TX
Antone L. Fourcroy - Fort Collins CO

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 106

US Classification:

327298

Abstract:

A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.

US Patent:

58156933, Sep 29, 1998

Filed:

Dec 15, 1995

Appl. No.:

8/572994

Inventors:

Mark W. McDermott - Austin TX
Antone L. Fourcroy - Fort Collins CO

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 104
G06F 108

US Classification:

395556

Abstract:

A processing system includes a clock synchromesh that receives indicia of critical activity from various functional units within the processing system and responsive to the indicia, ratchets down/up the frequency of a clock output signal to at least one of the functional units to reduce power consumption. The determination of critical activity is preferably made according to a heuristic internal to a processor under software or hardware control.

US Patent:

58601058, Jan 12, 1999

Filed:

Nov 13, 1995

Appl. No.:

8/557977

Inventors:

Mark W. McDermott - Austin TX
Robert W. French - Austin TX
Antone L. Fourcroy - Ft. Collins CO
Mark E. Burchfield - Austin TX
Xiaoli Y. Mendyke - Plano TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711135

Abstract:

An NDIRTY cache line lookahead technique is used to expedite cache flush and export operations by providing a mechanism to avoid scanning at least some cache lines that do not contain dirty data (and therefore will not have to be exported). The exemplary cache organization uses one-line lookahead where each cache line but the last has associated with it an NDIRTY bit that indicates whether the next cache line contains dirty data. For cache flush and export operations, when a cache line (N) is read to check for dirty data that must be exported, the NDIRTY bit for that cache line is also tested to determine whether the next cache line (N+1) contains dirty data--if the NDIRTY bit is clear, indicating that the next cache line is clean, then that line is skipped and the scan proceeds with the line after that (N+2). This exemplary one-line lookahead implementation is readily extendible to N-line lookahead. The cache line lookahead technique reduces the number of cache line accesses required during flush/export operations, with the attendant advantages of reduced flush/export penalty cycles and power, thereby improving overall system performance.