Mark R O'Brien

US Patent:

20180203971, Jul 19, 2018

Filed:

Jan 18, 2017

Appl. No.:

15/409152

Inventors:

- Redwood Shores CA, US
Aparna Ramachandran - Cupertino CA, US
James Ballard - Palo Alto CA, US
Mark Russell O'brien - Irvine CA, US
Sampanna Prashant Pathak - Santa Clara CA, US

International Classification:

G06F 17/50

Abstract:

A method may include obtaining a design including cells and a power grid. The method may further include dividing the design into tiles, determining a voltage budget for a tile, calculating a voltage drop for each cell of the tile based on determining an activity factor for the cell and a peak current consumed by the cell, determining, for each cell of the tile and based on the power grid, an affected vicinity for the cell including one or more neighboring cells affected by a current drawn on the cell, determining an affected vicinity for the tile based on the affected vicinity for each cell of the subset, calculating a voltage drop for the tile based on the voltage drop for each cell of the affected vicinity for the tile, and detecting a voltage deviation when a difference between the voltage budget and the voltage drop exceeds a threshold.