Martin D Frank

US Patent:

7105889, Sep 12, 2006

Filed:

Jun 4, 2004

Appl. No.:

10/863830

Inventors:

Cyril Cabral, Jr. - Mahopac NY, US
Eduard A. Cartier - New York NY, US
Matthew W. Copel - Yorktown Heights NY, US
Martin M. Frank - New York NY, US
Evgeni P. Gousev - Mahopac NY, US
Supratik Guha - Chappaqua NY, US
Rajarao Jammy - Hopewell Junction NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/792

US Classification:

257324, 257369, 257411

Abstract:

A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlON. The high k dielectric can be HfO, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/HOperoxide solution.

US Patent:

7242055, Jul 10, 2007

Filed:

Nov 15, 2004

Appl. No.:

10/988733

Inventors:

Cyril Cabral, Jr. - Mahopac NY, US
Eduard A. Cartier - New York NY, US
Martin M. Frank - New York NY, US
Evgeni P. Gousev - Mahopac NY, US
Supratik Guha - Chappaqua NY, US
Paul C. Jamison - Hopewell Junction NY, US
Rajarao Jammy - Hopewell Junction NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/792

US Classification:

257324, 257402, 257491, 438216, 438287

Abstract:

A semiconductor structure is provided that includes a Vstabilization layer between a gate dielectric and a gate electrode. The Vstabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vstabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

US Patent:

7368045, May 6, 2008

Filed:

Jan 27, 2005

Appl. No.:

11/050790

Inventors:

Philippe M. Vereecken - Sleepy Hollow NY, US
Veeraraghavan S. Basker - Yorktown Heights NY, US
Cyril Cabral, Jr. - Mahopac NY, US
Emanuel I. Cooper - Scarsdale NY, US
Hariklia Deligianni - Tenafly NJ, US
Martin M. Frank - New York NY, US
Rajarao Jammy - Hopewell Junction NY, US
Vamsi Krishna Paruchuri - New York NY, US
Katherine L. Saenger - Ossining NY, US
Xiaoyan Shao - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C25D 5/02
C25D 11/04

US Classification:

205118, 205324

Abstract:

A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

US Patent:

7452767, Nov 18, 2008

Filed:

Aug 7, 2006

Appl. No.:

11/500254

Inventors:

Cyril Cabral, Jr. - Mahopac NY, US
Eduard A. Cartier - New York NY, US
Matthew W. Copel - Yorktown Heights NY, US
Martin M. Frank - New York NY, US
Evgeni P. Gousev - Mahopac NY, US
Supratik Guha - Chappaqua NY, US
Rajarao Jammy - Hopewell Junction NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238

US Classification:

438216, 438199, 438261, 438287, 438591, 438785, 257E21202, 257E21639

Abstract:

A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlON. The high k dielectric can be HfO, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/HOperoxide solution.

US Patent:

7479683, Jan 20, 2009

Filed:

Oct 1, 2004

Appl. No.:

10/957342

Inventors:

Cyril Cabral, Jr. - Mahopac NY, US
Eduard A. Cartier - New York NY, US
Matthew W. Copel - Yorktown Heights NY, US
Martin M. Frank - New York NY, US
Evgeni P. Gousev - Mahopac NY, US
Supratik Guha - Chappaqua NY, US
Rajarao Jammy - Hopewell Junction NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/94
H01L 29/76

US Classification:

257410, 257368, 257369, 257528, 257E21636, 257E21639, 438107, 438592

Abstract:

The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first stack of a pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET device is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

US Patent:

7521346, Apr 21, 2009

Filed:

Oct 19, 2007

Appl. No.:

11/875524

Inventors:

Alessandro C. Callegari - Yorktown Heights NY, US
Martin M. Frank - New York NY, US
Rajarao Jammy - Hopewell Junction NY, US
Dianne L. Lacey - Mahopac NY, US
Fenton R. McFeely - Ossining NY, US
Sufi Zafar - Briarcliff Manor NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438592, 438591, 438648, 438685, 257411, 257412

Abstract:

A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4. 0 to about 4. 5, preferably about 4. 3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000 C. ), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

US Patent:

7521376, Apr 21, 2009

Filed:

Oct 26, 2005

Appl. No.:

11/259165

Inventors:

Martin M. Frank - Bronx NY, US
Steven J. Koester - Ossining NY, US
John A. Ott - Greenwood Lake NY, US
Huiling Shang - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/469

US Classification:

438778, 438758, 438765

Abstract:

A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

US Patent:

7560361, Jul 14, 2009

Filed:

Aug 12, 2004

Appl. No.:

10/917055

Inventors:

Martin M. Frank - New York NY, US
Alexander Reznicek - Mount Kisco NY, US
Evgeni P. Gousev - Mahopac NY, US
Eduard A. Cartier - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/447

US Classification:

438455, 438591, 438287, 257411, 257E21122

Abstract:

A method of forming a gate stack for semiconductor electronic devices utilizing wafer bonding of at least one structure containing a high-k dielectric material is provided. The method of the present invention includes a step of first selecting a first and second structure having a major surface respectively. In accordance with the present invention, at least one, or both, of the first and second structures includes at least a high-k dielectric material. Next, the major surfaces of the first and second structures are bonded together to provide a bonded structure containing at least the high-k dielectric material of a gate stack.