Matthew Scott Martin

US Patent:

20190392899, Dec 26, 2019

Filed:

Jun 20, 2018

Appl. No.:

16/013631

Inventors:

- Chandler AZ, US
Matthew G. Martin - Gilbert AZ, US
Gilles Festes - Fuveau, FR

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 16/04
G11C 11/4074
G11C 11/56
H01L 27/11521
H01L 29/66

Abstract:

Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positive or negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating a split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltage to the word line, applying a second non-zero voltage to the bit line, and applying a third non-zero voltage Vto the control gate.