Matthew J Mitchell

US Patent:

53090373, May 3, 1994

Filed:

Jul 8, 1992

Appl. No.:

7/910194

Inventors:

Lawrence D. Curley - Endwell NY
Matthew J. Mitchell - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

3072723

Abstract:

A power-on reset circuit is used to initialize a system component upon power-on. The circuit comprises a digital circuit such as a shift register which exhibits a multiplicity of uncertain or random outputs upon power-on. These output are coupled to digital logic such as an AND gate which itself outputs a power-on reset signal when any of the outputs of the shift register is not a predetermined output level. Because the outputs of the shift register are uncertain or arbitrary upon power-on and there are a multiplicity of such outputs, it is not likely that all of the outputs of the shift register will coincidentally exhibit the predetermined levels upon power-on. Consequently, it is very likely that the AND gate will provide the power-on reset signal upon power-on to initialize the system component. Subsequently, when the system is ready for normal operation, the shift register is set with the predetermined levels to terminate the power-on reset signal and thereby enable or condition the system component for normal operation.

US Patent:

54106559, Apr 25, 1995

Filed:

Sep 13, 1994

Appl. No.:

8/305502

Inventors:

James D. Greenfield - Binghamton NY
Matthew J. Mitchell - Endicott NY
William R. Taylor - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 300
G06F 1312

US Classification:

395275

Abstract:

An apparatus for intersystem I/O channel paging. The I/O channel through an I/O channel adapter provides communication between a central processor, an I/O processor, and a shared electronic storage device. The central processor and I/O processor are each enabled for recognizing specific instructions. The intersystem channel may be implemented in the form of a page chain table. Either process is capable of constructing a page chain table in the shared electronic storage device, upon receipt of appropriate instructions. The central processor or I/O processor signals the I/O channel adapter with identification of a page chain table to select. The I/O channel adapter fetches table entries and executes the table. The I/O channel adapter initiates I/O activity upon execution of the table. The I/O channel is not dependent upon the central processor or I/O processor for fetching or executing instructions, rather it acts independent of the processors once the page chain table is created.

US Patent:

41551176, May 15, 1979

Filed:

Jul 28, 1977

Appl. No.:

5/819913

Inventors:

Matthew J. Mitchell - Endicott NY
Howard L. Page - Apalachin NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 304

US Classification:

364200

Abstract:

A high performance channel-to-channel adapter for interconnecting two or more digital computers or digital data processors. Multiple input/output device addresses are recognized by the channel-to-channel adapter. The channel-to-channel adapter makes the proper processor-to-processor connection by matching device addresses. In particular, it interconnects for data transfer purposes the two processors for which the same device address has been received. The assignment of device addresses for processor use and the direction of data transfer are by conventions agreed to among the software systems executing on the interconnected processors. The channel-to-channel adapter does not have a view of these conventions. In the more general case, two device addresses are assigned by software convention to each processor-to-processor link, one address being used to transfer data in one direction and the other address being used to transfer data in the opposite direction.

US Patent:

40486710, Sep 13, 1977

Filed:

Jun 30, 1976

Appl. No.:

5/701400

Inventors:

Robert William Callahan - Endwell NY
Paul Eugene Kauffman - Endwell NY
Matthew Joseph Mitchell - Endicott NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

G06F 906
G06F 916
G06F 1300

US Classification:

364200

Abstract:

Apparatus for signalling the occurrence of a match between an address that is supplied to a control store and an address that is to be watched for in a data processing system that executes several instruction streams concurrently. The apparatus signals the occurrence of a storage accessing operation at a location that is uniquely identified only by a virtual address that is longer than the actual address used in accessing the store. Means is provided for comparing the actual address used in accessing the store with the corresponding portion of the complete address, and means is provided for recording the location of an address to be watched for in a particular frame of the store and for signalling a match that occurs in such a frame. The apparatus is useful for testing the operation of the data processing system by relating a recurring malfunction of the system to the execution of an instruction at the address that is watched for.

US Patent:

20140088589, Mar 27, 2014

Filed:

Nov 26, 2013

Appl. No.:

14/090223

Inventors:

- Memphis TN, US
Matthew E. Mitchell - Pelham NH, US
Karen Drucker - Danville NH, US
Kobi Iki - San Carlos CA, US

International Classification:

A61B 18/12

US Classification:

606 34

Abstract:

A method and apparatus include determining a value of a parameter associated with operation of an electrosurgical probe having a particular probe design, and determining whether the value of the parameter is within a range of values that has been predetermined for the particular probe design to indicate that the probe is treating tissue in a desired manner. Power is delivered to the probe according to an algorithm based upon a determination that the value of the parameter is outside the range of values The algorithm delivers power in a pulsed profile including portions of low power and portions of high power. In one embodiment, the tissue treatment is ablation, the parameter is impedance, and the method limits tissue necrosis to less than 200 microns. In another embodiment, the tissue treatment is shrinkage, the parameter is temperature, and the method limits power delivery when the probe is not shrinking tissue.