Michael T Ferrara

US Patent:

20200204501, Jun 25, 2020

Filed:

Feb 28, 2020

Appl. No.:

16/804960

Inventors:

- Santa Clara CA, US
Patrick BOSSHART - Plano TX, US
Jay Evan Scott PETERSON - San Francisco CA, US
Michael Gregory FERRARA - Palo Alto CA, US
Steven Licking - San Jose CA, US
Chaitanya Kodeboyina - Los Altos CA, US

International Classification:

H04L 12/931
H04L 12/00

Abstract:

A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

US Patent:

20180234355, Aug 16, 2018

Filed:

Feb 4, 2018

Appl. No.:

15/888050

Inventors:

- Santa Clara CA, US
Patrick Bosshart - Plano TX, US
Jay Evan Scott Peterson - San Francisco CA, US
Michael Gregory Ferrara - Palo Alto CA, US
Steven Licking - San Jose CA, US
Chaitanya Kodeboyina - Los Altos CA, US

International Classification:

H04L 12/931
H04L 12/00
H04L 12/26

Abstract:

A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

US Patent:

20170093986, Mar 30, 2017

Filed:

Sep 24, 2015

Appl. No.:

14/863961

Inventors:

- Palo Alto CA, US
Patrick Bosshart - Plano TX, US
Jay Evan Scott Peterson - San Francisco CA, US
Michael Gregory Ferrara - Palo Alto CA, US
Steven Licking - San Jose CA, US
Chaitanya Kodeboyina - Los Altos CA, US

International Classification:

H04L 29/08

Abstract:

A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.