Michael M Lo

US Patent:

8429616, Apr 23, 2013

Filed:

Mar 19, 2010

Appl. No.:

12/728067

Inventors:

Jasdeep Singh Sahni - San Jose CA, US
Anil Madan - San Jose CA, US
Deepak Seetharam Nadig - San Jose CA, US
Po Cheung - San Jose CA, US
Bhavesh Mistry - San Jose CA, US
John Bodine - Mountain View CA, US
Michael Lo - San Francisco CA, US

Assignee:

eBay Inc. - San Jose CA

International Classification:

G06F 9/44

US Classification:

717124, 717125, 717126, 717127, 717128, 717129, 717130, 717131, 717132, 717133, 717134, 717135

Abstract:

Various embodiments include at least one of systems, methods, and software to receive input configuring tests within a computing environment to expose users to standard application or website experiences or test experiences. In some embodiments, multiple tests may be configured to run orthogonally within user experiences without affecting the results of one another. Some such embodiments preserve the ability to execute certain tests in a non-orthogonal manner while other tests are allowed to execute orthogonally.

US Patent:

20130239091, Sep 12, 2013

Filed:

Apr 22, 2013

Appl. No.:

13/867203

Inventors:

Jasdeep Singh Sahni - San Jose CA, US
Anil Madan - San Jose CA, US
Deepak Seetharam Nadig - San Jose CA, US
Po Cheung - San Jose CA, US
Bhavesh Mistry - San Jose CA, US
John Bodine - Mountain View CA, US
Michael Lo - San Francisco CA, US

Assignee:

eBay Inc. - San Jose CA

International Classification:

G06F 11/36

US Classification:

717124

Abstract:

Various embodiments include at least one of systems, methods, and software to receive input configuring tests within a computing environment to expose users to standard application or website experiences or test experiences. In some embodiments, multiple tests may be configured to run orthogonally within user experiences without affecting the results of one another. Some such embodiments preserve the ability to execute certain tests in a non-orthogonal manner while other tests are allowed to execute orthogonally.

US Patent:

20230101211, Mar 30, 2023

Filed:

Dec 1, 2022

Appl. No.:

18/073254

Inventors:

- Redwood City CA, US
Kathryn Mary PASWATERS - San Francisco CA, US
Casey Teal LANDEY - San Francisco CA, US
Akira Bryan UEDA - San Francisco CA, US
Jeffrey WEINTRAUB - San Francisco CA, US
Kenneth CHOU - Oakland CA, US
Michael LO - San Francisco CA, US
Nicolas DIBENEDETTO - San Francisco CA, US

International Classification:

A61B 34/37
A61B 34/00

Abstract:

A medical instrument drive assembly includes a base portion, a first set of one or more drive outputs, a platform secured to the base portion, and a latching mechanism. The first set of one or more drive outputs are coupled to and/or extending from the base portion and are configured to drive a first medical instrument. The platform is secured to the base portion and movable between an elevated configuration and a depressed configuration. The platform is biased in the elevated configuration. The latching mechanism is configured to cause the platform to be held in the depressed configuration.

US Patent:

20210343331, Nov 4, 2021

Filed:

Jul 16, 2021

Appl. No.:

17/377799

Inventors:

- San Diego CA, US
Yanru LI - San Diego CA, US
Michael Hawjing LO - San Diego CA, US
Dexter Tamio CHUN - San Diego CA, US

International Classification:

G11C 11/406
G11C 7/10

Abstract:

In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

US Patent:

20210064463, Mar 4, 2021

Filed:

Jul 30, 2020

Appl. No.:

16/944110

Inventors:

- San Diego CA, US
Michael Hawjing LO - San Diego CA, US
Dexter Tamio CHUN - San Diego CA, US
Xavier Loic LELOUP - San Diego CA, US
Laurent Rene MOLL - San Jose CA, US

International Classification:

G06F 11/10
G06F 3/06

Abstract:

Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

US Patent:

20210065772, Mar 4, 2021

Filed:

Jul 31, 2020

Appl. No.:

16/945303

Inventors:

- San Diego CA, US
Michael Hawjing LO - San Diego CA, US
Dexter Tamio CHUN - San Diego CA, US
Xavier Loic LELOUP - San Diego CA, US
Laurent Rene MOLL - San Jose CA, US

International Classification:

G11C 11/4074
G11C 11/409

Abstract:

Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

US Patent:

20210032958, Feb 4, 2021

Filed:

Feb 21, 2020

Appl. No.:

16/797489

Inventors:

- Missouri City TX, US
Stephen Parks - Houston TX, US
Michael Lo - Missouri City TX, US

International Classification:

E21B 34/06
E21B 33/14

Abstract:

A toe sleeve that is configured to disconnect from casing. More specifically, a toe sleeve that is configured to shear from casing creating a dynamic opening that does not get plugged.

US Patent:

20200321051, Oct 8, 2020

Filed:

Jun 19, 2020

Appl. No.:

16/907103

Inventors:

- San Diego CA, US
Yanru LI - San Diego CA, US
Michael Hawjing LO - San Diego CA, US
Dexter Tamio CHUN - San Diego CA, US

International Classification:

G11C 11/406
G11C 7/10

Abstract:

In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Address:

5050 Ambassador Way APT 306, Houston, TX 77056

Phone:

(713)6213123

VIN:

WDBUF22X08B214300

Make:

MERCEDES-BENZ

Model:

E-CLASS

Year:

2008