Michael W Lo

US Patent:

60789182, Jun 20, 2000

Filed:

Apr 2, 1998

Appl. No.:

9/054178

Inventors:

Bradley P. Allen - Manhattan Beach CA
Jeffrey M. Greif - Venice CA
David L. Adam - San Francisco CA
John B. Jensen - Hermosa Beach CA
Michael W. Lo - Marina Del Rey CA
Cormac Twomey - Marina Del Rey CA

Assignee:

Trivada Corporation - Culver City CA

International Classification:

G06F 1700

US Classification:

707 6

Abstract:

One embodiment of the present invention provides a system for making predictions about data records from an incoming stream of data records. This system operates by discovering predictive relationships in an online manner between fields in records in the incoming stream of data records as the incoming stream of data records is received. These predictive relationships can used to predict values in fields based on other field values in the same record. This facilitates cleansing of data by allowing transaction values to be validated based upon predictions made from other field values in the same transaction record. It also allows missing field values to be predicted based upon the other field values. A variation of this embodiment provides for filtering transaction records based upon discovered predictive relationships and routing the transaction records to other servers in real-time. Another embodiment forms association rules between fields in records in the incoming stream of records, and outputs these association rules for viewing by a human decision-maker.

US Patent:

20210343331, Nov 4, 2021

Filed:

Jul 16, 2021

Appl. No.:

17/377799

Inventors:

- San Diego CA, US
Yanru LI - San Diego CA, US
Michael Hawjing LO - San Diego CA, US
Dexter Tamio CHUN - San Diego CA, US

International Classification:

G11C 11/406
G11C 7/10

Abstract:

In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

US Patent:

20210064463, Mar 4, 2021

Filed:

Jul 30, 2020

Appl. No.:

16/944110

Inventors:

- San Diego CA, US
Michael Hawjing LO - San Diego CA, US
Dexter Tamio CHUN - San Diego CA, US
Xavier Loic LELOUP - San Diego CA, US
Laurent Rene MOLL - San Jose CA, US

International Classification:

G06F 11/10
G06F 3/06

Abstract:

Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

US Patent:

20210065772, Mar 4, 2021

Filed:

Jul 31, 2020

Appl. No.:

16/945303

Inventors:

- San Diego CA, US
Michael Hawjing LO - San Diego CA, US
Dexter Tamio CHUN - San Diego CA, US
Xavier Loic LELOUP - San Diego CA, US
Laurent Rene MOLL - San Jose CA, US

International Classification:

G11C 11/4074
G11C 11/409

Abstract:

Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

US Patent:

20200321051, Oct 8, 2020

Filed:

Jun 19, 2020

Appl. No.:

16/907103

Inventors:

- San Diego CA, US
Yanru LI - San Diego CA, US
Michael Hawjing LO - San Diego CA, US
Dexter Tamio CHUN - San Diego CA, US

International Classification:

G11C 11/406
G11C 7/10

Abstract:

In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

US Patent:

20200278802, Sep 3, 2020

Filed:

Feb 27, 2020

Appl. No.:

16/803977

Inventors:

- San Diego CA, US
Dexter Tamio Chun - San Diego CA, US
Michael Hawjing Lo - San Diego CA, US
Shyamkumar Thoziyoor - San Diego CA, US
Ravindra Kumar - San Diego CA, US

International Classification:

G06F 3/06
G06F 12/0875

Abstract:

Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

US Patent:

20190379695, Dec 12, 2019

Filed:

Jun 9, 2018

Appl. No.:

16/004357

Inventors:

- Mountain View CA, US
Michael Lo - Culver City CA, US
Srini Chillappa - Culver City CA, US
Simon Tiku - Culver City CA, US
Viral Mehta - Culver City CA, US
John Meehan - Culver City CA, US

International Classification:

H04L 29/06
G06F 21/62

Abstract:

The disclosed computer-implemented method for detecting unauthorized data shares may include (1) providing a user of an anonymized inbox with an email alias to use for a particular online entity, (2) identifying one or more emails sent to the email alias from one or more different entities that are different from the particular online entity, (3) determining, based on the one or more emails having been sent by the different entities, that the particular online entity has shared the user's email alias with other entities, and (4) creating a privacy score for the particular online entity based at least in part on the determination that the particular online entity has shared the user's email alias with other entities. Various other methods, systems, and computer-readable media are also disclosed.

US Patent:

20190221252, Jul 18, 2019

Filed:

Mar 22, 2019

Appl. No.:

16/362427

Inventors:

- San Diego CA, US
Yanru LI - San Diego CA, US
Michael Hawjing LO - San Diego CA, US
Dexter Tamio CHUN - San Diego CA, US

International Classification:

G11C 11/406
G11C 7/10

Abstract:

In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.