Michael K Mcgowan

US Patent:

51592053, Oct 27, 1992

Filed:

Oct 24, 1990

Appl. No.:

7/603900

Inventors:

James L. Gorecki - Vail AZ
Michael J. McGowan - Tuscon AZ

Assignee:

Burr-Brown Corporation - Tucson AZ

International Classification:

H03K 5159
H03K 700
H03K 301
H03K 1700

US Classification:

307269

Abstract:

A circuit for generating a plurality of timing signals includes a plurality of cascade-connected delay cells, each having an input coupled to an output of another, and a plurality of latches. Set inputs of various latches are coupled to outputs of various delay cells to determine times of occurrence of leading edges of various timing pulses. Reset inputs of the various latches are coupled to outputs of various delay cells to determine times of occurrence of trailing edges of various timing pulses. The circuit includes a phase detector having a first input coupled to receive a clock signal and a second input coupled to an output of one of the delay cells to receive a signal indicative of propagation of a logic state through a first group of the delay cells, to produce an adjustment signal indicative of whether the phase of the indicator signal is ahead of or behind the phase of the clock signal. Each of the delay cells increases or decreases propagation time through that delay cell in response to the adjustment signal, so as to cause a time required for the logic state to propagate through all of the delay cells to be equal to a period of the clock signal.

US Patent:

50498827, Sep 17, 1991

Filed:

Dec 20, 1990

Appl. No.:

7/630539

Inventors:

James L. Gorecki - Vail AZ
Michael J. McGowan - Tucson AZ

Assignee:

Burr-Brown Corporation - Tucson AZ

International Classification:

H03M 136
H03M 138

US Classification:

341143

Abstract:

High speed conversion of an analog input signal to a digital output signal is performed by applying the analog input to an input of a unity gain amplifier. During a first pass, an output signal produced by the amplifier is applied to inputs of each of a plurality of comparators. A first group of successively larger reference voltages are applied to reference inputs of the comparators, respectively. A plurality of the comparators switch in response thereto to produce output signals indicative of a range within which the output of the amplifier lies. The outputs of the comparators are encoded to effectuate conversion thereof to an analog representation of the amplifier output. The analog representation is compared to the analog input signal and the difference therebetween is applied to the input of the amplifier. During another pass another group of reference voltages, each substantially lower than corresponding values thereof during the previous pass, are applied to the reference inputs of the comparators. Binary representations of the outputs of the comparators during each of the passes are combined into a binary word accurately representing the analog input signal.