Michael R Morrow

US Patent:

6624535, Sep 23, 2003

Filed:

Feb 17, 2001

Appl. No.:

09/785920

Inventors:

Michael W. Morrow - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02J 734

US Classification:

307 71, 307 43, 307 48, 307 85

Abstract:

A plurality of the voltage sources may be selectively connectable in a variety of different arrangements using a switch array whose connections are determined by a programmable controller. For example, a desired output voltage may be automatically provided by altering the connections between the voltage sources to achieve the desired voltage. A programmable controller may determine how to connect the voltage sources to achieve the desired output voltage.

US Patent:

6664775, Dec 16, 2003

Filed:

Aug 21, 2000

Appl. No.:

09/643082

Inventors:

Lawrence T. Clark - Phoenix AZ
Michael W. Morrow - Chandler AZ
Gregory B. Tucker - Chandler AZ
Yuan-Po Ypt Tseng - Chandler AZ
Ali Minaei - Chandler AZ
Jay Heeb - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02J 312

US Classification:

323351, 323354, 323284, 323286

Abstract:

Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

US Patent:

6898718, May 24, 2005

Filed:

Sep 28, 2001

Appl. No.:

09/967377

Inventors:

Michael W. Morrow - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F001/26

US Classification:

713320, 713300, 713322, 713323, 713324

Abstract:

Briefly, in accordance with one embodiment of the invention, a portable communication device has a processing unit and a monitoring unit. The monitoring unit monitors performance of a software process while the process is executing. If the process is executing inefficiently, the processing unit may alter power consumption of the portable communication device.

US Patent:

6949918, Sep 27, 2005

Filed:

Jun 10, 2003

Appl. No.:

10/459310

Inventors:

Lawrence T. Clark - Phoenix AZ, US
Michael W. Morrow - Chandler AZ, US
Gregory B. Tucker - Chandler AZ, US
Yuan-Po Ypt Tseng - Chandler AZ, US
Ali Minaei - Chandler AZ, US
Jay Heeb - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F001/40
G05F001/44

US Classification:

323351, 323354, 323284

Abstract:

Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

US Patent:

7039763, May 2, 2006

Filed:

Apr 11, 2003

Appl. No.:

10/411725

Inventors:

Dennis M. O'Connor - Chandler AZ, US
Michael W. Morrow - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711129, 711130

Abstract:

Briefly, in accordance with an embodiment of the invention, an apparatus and method to share a cache memory is provided. The method may include dynamically partitioning a cache memory to cache data for one or more active clients during operation of the cache memory, wherein the number of active clients varies during operation of the cache memory. The apparatus may include a control device coupled to a cache memory to dynamically partition the cache memory.

US Patent:

7120714, Oct 10, 2006

Filed:

May 27, 2003

Appl. No.:

10/445533

Inventors:

Dennis M. O'Connor - Chandler AZ, US
Michael W. Morrow - Chandler AZ, US
Stephen Strazdus - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/14
G06F 13/00
G06F 13/36
G06F 13/362

US Classification:

710243, 710240, 710241, 710244, 710111, 710113, 710116

Abstract:

A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requestors in accordance with a first arbitration scheme and a second-stage arbiter to grant one of the remaining requests in accordance with a second arbitration scheme. The first arbitration scheme may be a fast arbitration scheme such as a fixed-priority scheme, and the second arbitration scheme may be a rotating priority-based arbitration scheme or a least-recently-granted arbitration scheme. The first-stage arbiter may operate in a first pipelined stage, and the second-stage arbiter may operate in a second pipelined stage. Two-stage arbitration may help improve access of lower-priority requestors in a pipelined system. In one embodiment, a rotating-priority arbitrator includes a pseudo-random number generator to generate an amount for rotating priorities prior to arbitration. The rotating-priority arbiter may use either a counter or linear-feedback shift register to rotate priorities of requests.

US Patent:

7162609, Jan 9, 2007

Filed:

Dec 3, 2003

Appl. No.:

10/726885

Inventors:

Michael W. Morrow - Chandler AZ, US
Dennis M. O'Connor - Chandler AZ, US
Desikan Iyadurai - Chandler AZ, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 12/10

US Classification:

711207, 711137

Abstract:

According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.

US Patent:

7240168, Jul 3, 2007

Filed:

Mar 10, 2004

Appl. No.:

10/799564

Inventors:

Dennis M. O'Connor - Chandler AZ, US
Michael W. Morrow - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

711150, 711151

Abstract:

Briefly, in accordance with an embodiment of the invention, a system and method to order memory operations is provided. The method may include using at least one signal to indicate that a particular kind of memory operation is not globally observable but is observable by at least one processor of the system. The system may include a processor to use at least one signal for memory consistency, wherein the at least one signal indicates that a particular kind of memory operation is not globally observable in the system but is observable by at least one processor of the system. Other embodiments are described and claimed.