Michael Lee Morrow

US Patent:

20120226888, Sep 6, 2012

Filed:

Feb 13, 2012

Appl. No.:

13/371506

Inventors:

Bohuslav Rychlik - San Diego CA, US
Thomas Andrew Sartorius - Raleigh NC, US
Michael William Morrow - Cary NC, US
Raymond P. Palma - Raleigh CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 12/10

US Classification:

711207, 711E12061

Abstract:

Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.

US Patent:

20130086359, Apr 4, 2013

Filed:

Sep 29, 2011

Appl. No.:

13/248329

Inventors:

Subrato K. De - San Diego CA, US
Michael W. Morrow - Wilkes Barre PA, US
Moinul H. Khan - San Diego CA, US
Mark Bapst - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 12/00
G06F 9/30

US Classification:

712205, 711154, 711E12001, 712E09016

Abstract:

Memory access instructions, such as load and store instructions, are processed in a processor-based system. Processor hardware pipeline configurations enable efficient performance of memory access instructions, such as a pipeline configuration that enables, for a memory access operation request by a register-operand based virtual machine, computation of the memory location corresponding to a virtual-machine register by extracting a bit-field from the virtual-machine instruction and accessing (load or store) the computed memory location that represents a virtual register of the virtual-machine, in a single pass through the pipeline. Thus this processor hardware pipeline configuration enables a virtual machine register read/write operation to be performed by a single hardware processor instruction through a single pass in the processor hardware pipeline, for a register-operand based virtual machine.