Michael Hoaminh Tang

US Patent:

7750386, Jul 6, 2010

Filed:

Nov 12, 2008

Appl. No.:

12/269507

Inventors:

Wei Tian - Bloomington MN, US
Venkatram Venkatasamy - Edina MN, US
Ming Sun - Eden Prairie MN, US
Michael Xuefei Tang - Bloomington MN, US
Insik Jin - Eagan MN, US
Dimitar V. Dimitrov - Edina MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H01L 29/76
H01L 21/8242

US Classification:

257296, 257300, 257311, 438239, 438253

Abstract:

A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer.

US Patent:

7786463, Aug 31, 2010

Filed:

May 20, 2008

Appl. No.:

12/123685

Inventors:

Xuguang Wang - Maple Grove MN, US
Shuiyuan Huang - Apple Valley MN, US
Dimitar V. Dimitrov - Edina MN, US
Michael Xuefei Tang - Bloomington MN, US
Song S. Xue - Edina MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H01L 45/00

US Classification:

257 2, 257E45002

Abstract:

Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell.

US Patent:

7800941, Sep 21, 2010

Filed:

Nov 18, 2008

Appl. No.:

12/272896

Inventors:

Young Pil Kim - Eden Prairie MN, US
Chulmin Jung - Eden Prairie MN, US
Insik Jin - Eagan MN, US
Michael Xuefei Tang - Bloomington MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G11C 11/15

US Classification:

365171, 365 55, 365 66, 365148

Abstract:

A memory apparatus having at least one memory cell set comprising a first spin torque memory cell electrically connected in series to a second spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The memory cell set itself is configured to switch between a high resistance state and a low resistance state. The memory apparatus also has at least one reference cell set comprising a third spin torque memory cell electrically connected in anti-series to a fourth spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The reference cell set itself has a reference resistance that is a midpoint of the high resistance state and the low resistance state of the memory cell set.

US Patent:

7826181, Nov 2, 2010

Filed:

Nov 12, 2008

Appl. No.:

12/269537

Inventors:

Michael Xuefei Tang - Bloomington MN, US
Ming Sun - Eden Prairie MN, US
Dimitar V. Dimitrov - Edina MN, US
Patrick Ryan - St. Paul MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G11B 5/33
G11B 5/127

US Classification:

3603241, 257E21001, 257E29323, 365151, 438 3, 438 48

Abstract:

A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer.

US Patent:

7842938, Nov 30, 2010

Filed:

Nov 12, 2008

Appl. No.:

12/269514

Inventors:

Venkatram Venkatasamy - Edina MN, US
Ming Sun - Eden Prairie MN, US
Michael Xuefei Tang - Bloomington MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H01L 47/00

US Classification:

257 4, 257E47001

Abstract:

A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed.

US Patent:

7881098, Feb 1, 2011

Filed:

Aug 26, 2008

Appl. No.:

12/198416

Inventors:

Haiwen Xi - Prior Lake MN, US
Hongyue Liu - Maple Grove MN, US
Michael Xuefei Tang - Bloomington MN, US
Antoine Khoueir - Apple Valley CA, US
Song S. Xue - Edina MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G11C 11/00

US Classification:

365158, 365 63, 365148

Abstract:

A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.

US Patent:

7936585, May 3, 2011

Filed:

Jul 13, 2009

Appl. No.:

12/502222

Inventors:

Wei Tian - Bloomington MN, US
Insik Jin - Eagan MN, US
Venugopalan Vaithyanathan - Bloomington MN, US
Haiwen Xi - Prior Lake MN, US
Michael Xuefei Tang - Bloomington MN, US
Brian Lee - Boston MA, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G11C 11/00

US Classification:

365148, 365163, 365175

Abstract:

A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.

US Patent:

7939188, May 10, 2011

Filed:

Jul 13, 2009

Appl. No.:

12/501632

Inventors:

Haiwen Xi - Prior Lake MN, US
Antoine Khoueir - Apple Valley MN, US
Brian Lee - Boston MA, US
Pat Ryan - St. Paul MN, US
Michael Tang - Bloomington MN, US
Insik Jin - Eagan MN, US
Paul E. Anderson - Eden Prairie MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G11B 5/39
H01F 10/08
H01L 43/08
H01L 43/12

US Classification:

4288111, 4288115, 36032411, 36032412, 3603242, 365158, 257421, 32420721

Abstract:

A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer.