Mingming M Xu

US Patent:

20160164704, Jun 9, 2016

Filed:

Feb 9, 2016

Appl. No.:

15/019835

Inventors:

- Santa Clara CA, US
Mingming XU - Phoenix AZ, US

International Classification:

H04L 25/03
H04L 7/033

Abstract:

Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.

US Patent:

20150249454, Sep 3, 2015

Filed:

Feb 28, 2014

Appl. No.:

14/194249

Inventors:

Stefano GIACONI - Phoenix AZ, US
Mingming XU - Phoenix AZ, US

International Classification:

H03L 7/081
H04L 7/033

Abstract:

Described is an apparatus which comprises: a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering; a switch capacitor network to integrate currents from the DAC, the switch capacitor network having switches which are controllable by a plurality of digital clock signals; an output stage to compare the integrated currents against at least two threshold voltages and to generate an output signal; and a duty cycle corrector (DCC) operable to adjust the at least two threshold voltages to modify duty cycle of the output signal.

US Patent:

20150188693, Jul 2, 2015

Filed:

Dec 27, 2013

Appl. No.:

14/142606

Inventors:

Stefano GIACONI - Phoenix AZ, US
Mingming XU - Phoenix AZ, US
Issy KIPNIS - Santa Clara CA, US

International Classification:

H04L 7/00
H04L 25/03
H04L 7/033

Abstract:

Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.

US Patent:

20150163077, Jun 11, 2015

Filed:

Feb 18, 2015

Appl. No.:

14/625529

Inventors:

Mingming XU - Phoenix AZ, US
Stefano Giacconi - Phoenix AZ, US

International Classification:

H04L 25/03

Abstract:

An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).

US Patent:

20140269889, Sep 18, 2014

Filed:

Mar 14, 2013

Appl. No.:

13/830244

Inventors:

Mingming Xu - Phoenix AZ, US
Stefano Giacconi - Phoenix AZ, US

International Classification:

H04L 25/03

US Classification:

375233

Abstract:

An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).