Mohammad Sayeed Hasan

US Patent:

20220415791, Dec 29, 2022

Filed:

Jun 24, 2021

Appl. No.:

17/357773

Inventors:

- Santa Clara CA, US
Michael James MAKOWSKI - Beaverton OR, US
Benjamin KRIEGEL - Portland OR, US
Robert JOACHIM - Beaverton OR, US
Desalegne B. TEWELDEBRHAN - Sherwood OR, US
Charles H. WALLACE - Portland OR, US
Tahir GHANI - Portland OR, US
Mohammad HASAN - Aloha OR, US

International Classification:

H01L 23/528
H01L 23/522
H01L 21/768

Abstract:

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a dielectric material structure having a trench therein. A conductive interconnect line in the trench, the conductive interconnect line having a length and a width, the width having a cross-sectional profile, wherein the cross-sectional profile of the width of the conductive interconnect line has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width.

US Patent:

20220406778, Dec 22, 2022

Filed:

Jun 21, 2021

Appl. No.:

17/353263

Inventors:

- Santa Clara CA, US
Biswajeet GUHA - Hillsboro OR, US
Mohit K. HARAN - Hillsboro OR, US
Mohammad HASAN - Aloha OR, US
Reken PATEL - Portland OR, US
Sean PURSEL - Hillsboro OR, US
Jake JAFFE - Portland OR, US

International Classification:

H01L 27/092
H01L 29/78
H01L 29/66
H01L 29/06

Abstract:

Integrated circuit structures having plugged metal gates, and methods of fabricating integrated circuit structures having plugged metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on the STI structure. The gate dielectric material layer and the conductive gate layer are along a side of the dielectric gate plug, and the gate dielectric material layer is in direct contact with an entirety of the side of the dielectric gate plug.

US Patent:

20220390990, Dec 8, 2022

Filed:

Jun 4, 2021

Appl. No.:

17/339001

Inventors:

- Santa Clara CA, US
Mohammad HASAN - Aloha OR, US
Charles H. WALLACE - Portland OR, US
Tahir GHANI - Portland OR, US
Robert JOACHIM - Beaverton OR, US
Shengsi LIU - Portland OR, US

International Classification:

G06F 1/18
H05K 1/11
G06F 1/16

Abstract:

Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. A conductive structure is in direct contact with one of the plurality of gate structures or with one of the plurality of conductive trench contact structures.

US Patent:

20220392808, Dec 8, 2022

Filed:

Jun 4, 2021

Appl. No.:

17/339160

Inventors:

- Santa Clara CA, US
Mohammad HASAN - Aloha OR, US
William HSU - Portland OR, US
Biswajeet GUHA - Hillsboro OR, US
Charles H. WALLACE - Portland OR, US
Tahir GHANI - Portland OR, US
Sean PURSEL - Hillsboro OR, US

International Classification:

H01L 21/8234
H01L 27/088
H01L 29/06
H01L 29/423
H01L 29/775
H01L 29/786
H01L 21/02
H01L 29/66

Abstract:

Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.

US Patent:

20220392898, Dec 8, 2022

Filed:

Jun 7, 2021

Appl. No.:

17/340429

Inventors:

- Santa Clara CA, US
Mohit K. HARAN - Hillsboro OR, US
Mohammad HASAN - Aloha OR, US
Biswajeet GUHA - Hillsboro OR, US
Alison V. DAVIS - Portland OR, US
Leonard P. GULER - Hillsboro OR, US

International Classification:

H01L 27/092
H01L 29/78
H01L 29/06
H01L 29/66

Abstract:

Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

US Patent:

20220199797, Jun 23, 2022

Filed:

Dec 22, 2020

Appl. No.:

17/131467

Inventors:

- Santa Clara CA, US
Willy Rachmady - Beaverton OR, US
Hsin-Fen Li - Hillsboro OR, US
Christopher Parker - Portland OR, US
Prashant Wadhwa - Portland OR, US
Tahir Ghani - Portland OR, US
Mohammad Hasan - Aloha OR, US
Jianqiang Lin - Santa Clara CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/423
H01L 29/786
H01L 29/417
H01L 27/088

Abstract:

A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.

US Patent:

20230095191, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/485149

Inventors:

- Santa Clara CA, US
Ryan Keech - Portland OR, US
Anand Murthy - Portland OR, US
Mohammad Hasan - Aloha OR, US
Pratik Patel - Portland OR, US
Tahir Ghani - Portland OR, US
Subrina Rafique - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/786
H01L 29/06
H01L 29/423
H01L 29/417
H01L 21/02
H01L 21/3065
H01L 29/66

Abstract:

Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.

US Patent:

20230088753, Mar 23, 2023

Filed:

Sep 23, 2021

Appl. No.:

17/482870

Inventors:

- Santa Clara CA, US
Aaron D. Lilak - Beaverton OR, US
Patrick Keys - Beaverton OR, US
Cory Weber - Hillsboro OR, US
Rishabh Mehandru - Portland OR, US
Anand S. Murthy - Portland OR, US
Biswajeet Guha - Hillsboro OR, US
Mohammad Hasan - Aloha OR, US
William Hsu - Portland OR, US
Tahir Ghani - Portland OR, US
Chang Wan Han - Hillsboro OR, US
Kihoon Park - Hillsboro OR, US
Sabih Omar - Hillsboro OR, US

International Classification:

H01L 29/10
H01L 29/06
H01L 29/423
H01L 29/786
H01L 21/02
H01L 21/74
H01L 29/66

Abstract:

Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.